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* Described the missing AVX forms of SSE2 convert instructionsBruno Cardoso Lopes2010-06-291-51/+200
| | | | llvm-svn: 107108
* Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding isBob Wilson2010-06-291-1/+1
| | | | | | the same as ARM except that the condition code field is always set to ARMCC::AL. llvm-svn: 107107
* Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo insteadBob Wilson2010-06-281-5/+7
| | | | | | of the Subtarget. llvm-svn: 107086
* tidy up style. no functional change.Jim Grosbach2010-06-281-2/+3
| | | | llvm-svn: 107073
* Refactor encoding function for NEON 1-register with modified immediate format.Bob Wilson2010-06-281-5/+1
| | | | llvm-svn: 107070
* Support Thumb mode encoding of NEON instructions.Bob Wilson2010-06-281-0/+15
| | | | llvm-svn: 107068
* Reduce indentation via early exit. NFC.Bill Wendling2010-06-281-100/+110
| | | | llvm-svn: 107067
* minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. ↵Jim Grosbach2010-06-283-68/+68
| | | | | | No functional change. llvm-svn: 106988
* use ArgOperand APIGabor Greif2010-06-261-5/+5
| | | | llvm-svn: 106946
* use ArgOperand APIGabor Greif2010-06-261-24/+24
| | | | llvm-svn: 106945
* use ArgOperand APIGabor Greif2010-06-262-8/+8
| | | | llvm-svn: 106944
* Followup to r106770: actually generate SXTB and SXTH for sign-extensions.Eli Friedman2010-06-261-5/+2
| | | | llvm-svn: 106940
* Add support for encoding NEON VMOV (from scalar to core register) instructions.Bob Wilson2010-06-261-0/+33
| | | | llvm-svn: 106938
* It's now possible to run code placement pass for ARM.Evan Cheng2010-06-261-4/+8
| | | | llvm-svn: 106935
* When creating X86 MUL8 and DIV8 instructions, make sure we don't produceJakob Stoklund Olesen2010-06-261-37/+49
| | | | | | | | | | | CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast register allocator. Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit). This fixes PR7312. llvm-svn: 106934
* Renumber NEON instruction formats to be consecutive.Bob Wilson2010-06-263-26/+24
| | | | llvm-svn: 106927
* Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm toBob Wilson2010-06-253-27/+27
| | | | | | "N..." instead of "NEON..." for consistency with the other NEON format names. llvm-svn: 106921
* Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructionsBruno Cardoso Lopes2010-06-251-0/+15
| | | | llvm-svn: 106917
* Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.Bob Wilson2010-06-253-22/+7
| | | | | | Renumber MiscFrm to 25. llvm-svn: 106916
* Reapply r106896:Bruno Cardoso Lopes2010-06-253-23/+115
| | | | | | | Add several AVX MOV flavors Support VEX encoding for MRMDestReg llvm-svn: 106912
* Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This wasDaniel Dunbar2010-06-251-2/+2
| | | | | | | | | introduced in r106343, but only showed up recently (with a particular compiler & linker combination) because of the particular check, and because we have no builtin checking for dereferencing the end of an array, which is truly unfortunate. llvm-svn: 106908
* revert this now, it's using avx instead of sse :)Bruno Cardoso Lopes2010-06-252-111/+19
| | | | llvm-svn: 106906
* Change if-conversion block size limit checks to add some flexibility.Evan Cheng2010-06-255-17/+57
| | | | llvm-svn: 106901
* Add support for encoding 3-register NEON instructions, and fixBob Wilson2010-06-251-3/+36
| | | | | | emitNEON2RegInstruction's handling of 2-address operands. llvm-svn: 106900
* Add several AVX MOV flavorsBruno Cardoso Lopes2010-06-252-19/+111
| | | | | | Support VEX encoding for MRMDestReg llvm-svn: 106896
* The hasMemory argument is irrelevant to how the argumentDale Johannesen2010-06-258-26/+7
| | | | | | | | | for an "i" constraint should get lowered; PR 6309. While this argument was passed around a lot, this is the only place it was used, so it goes away from a lot of other places. llvm-svn: 106893
* Add support for encoding 2-register NEON instructions.Bob Wilson2010-06-251-3/+25
| | | | llvm-svn: 106891
* pcmpeqd and friends are Commutable.Dan Gohman2010-06-251-3/+3
| | | | llvm-svn: 106886
* Fix indentation.Bob Wilson2010-06-251-1/+1
| | | | llvm-svn: 106881
* - Reapply r106066 now that the bzip2 build regression has been fixed.Bill Wendling2010-06-251-0/+20
| | | | | | - 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878. llvm-svn: 106880
* Move the last piece of SSE2 convert instructions to the Convert Instructions ↵Bruno Cardoso Lopes2010-06-251-150/+151
| | | | | | section llvm-svn: 106877
* More SSE refactoring, this time with different types of MOVsBruno Cardoso Lopes2010-06-251-160/+125
| | | | llvm-svn: 106876
* IT instructions are considered to be scheduling hazards, but are scheduledJim Grosbach2010-06-251-1/+13
| | | | | | | | | | | | with the following instructions. This is done via trickery by considering the instruction preceding the IT to be the hazard. Care must be taken to ensure it's the first non-debug instruction, or the presence of debug info will affect codegen. Part of the continuing work for rdar://7797940, making ARM code-gen unaffected by the presence of debug information. llvm-svn: 106871
* Refactoring of more SSE conversion instructions. Also add some AVX ↵Bruno Cardoso Lopes2010-06-251-105/+93
| | | | | | instrinsics Int_V... placeholders llvm-svn: 106867
* Add missing ARM and Thumb data layout info for vector types.Bob Wilson2010-06-251-4/+8
| | | | | | Radar 8128745. llvm-svn: 106820
* Reduce indentation.Bob Wilson2010-06-251-8/+7
| | | | llvm-svn: 106819
* Add some AVX convert instructionsBruno Cardoso Lopes2010-06-251-0/+24
| | | | llvm-svn: 106815
* Refactoring of SSE convert intrinsicsBruno Cardoso Lopes2010-06-241-62/+53
| | | | llvm-svn: 106808
* Refactoring of SSE conversion instructionsBruno Cardoso Lopes2010-06-241-25/+18
| | | | llvm-svn: 106804
* Refactor SSE cmp intrinsics and declare the same for AVXBruno Cardoso Lopes2010-06-241-30/+29
| | | | llvm-svn: 106796
* - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.Bruno Cardoso Lopes2010-06-242-164/+138
| | | | | | | - Fix a small VEX encoding issue. - Move compare instructions to their appropriate place. llvm-svn: 106787
* Disallow matching "i" constraint to symbol addresses whenDale Johannesen2010-06-241-0/+7
| | | | | | | | | | | | address requires a register or secondary load to compute (most PIC modes). This improves "g" constraint handling. 8015842. The test from 2007 is attempting to test the fix for PR1761, but since -relocation-model=static doesn't work on Darwin x86-64, it was not testing what it was supposed to be testing and was passing erroneously. Fixed to use Linux x86-64. llvm-svn: 106779
* Oops. IT block formation pass needs to be run at any optimization level.Evan Cheng2010-06-241-4/+3
| | | | llvm-svn: 106775
* Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.Eli Friedman2010-06-241-11/+9
| | | | llvm-svn: 106770
* PR7458: Try commuting Thumb2 instruction operands to put them into 2-addressBob Wilson2010-06-241-3/+11
| | | | | | form so they can be narrowed to 16-bit instructions. llvm-svn: 106762
* Reapply r106634, now that the bug it exposed is fixed.Dan Gohman2010-06-241-2/+4
| | | | llvm-svn: 106746
* Teach the x86 mc assembler that %dr6 = %db6, this implementsChris Lattner2010-06-242-0/+54
| | | | | | rdar://8013734 llvm-svn: 106725
* more cleanupsChris Lattner2010-06-241-21/+15
| | | | llvm-svn: 106724
* reduce indentationChris Lattner2010-06-241-20/+15
| | | | llvm-svn: 106723
* fix breakage from r98938 by correctly marking msp430 calls as variadic.Chris Lattner2010-06-241-1/+1
| | | | | | Patch by Ben Ransford! llvm-svn: 106722
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