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* AMDGPU: fdiv -1, x -> rcp -xMatt Arsenault2016-08-021-16/+25
| | | | llvm-svn: 277535
* [Hexagon] Recognize vcombine in copy propagationKrzysztof Parzyszek2016-08-021-2/+8
| | | | llvm-svn: 277528
* [NVPTX] remove unnecessary named metadata update that happens to break debug ↵Artem Belevich2016-08-021-36/+0
| | | | | | | | | | info. Also added test case to verify IR changes done by NVPTXGenericToNVVM pass. Differential Revision: https://reviews.llvm.org/D22837 llvm-svn: 277520
* AArch64: properly calculate cmpxchg status in FastISel.Tim Northover2016-08-022-13/+28
| | | | | | | | | | | | We were relying on the misleadingly-names $status result to actually be the status. Actually it's just a scratch register that may or may not be valid (and is the inverse of the real ststus anyway). Success can be determined by comparing the value loaded against the one we wanted to see for "cmpxchg strong" loops like this. Should fix PR28819. llvm-svn: 277513
* AMDGPU: Stay in WQM for non-intrinsic storesNicolai Haehnle2016-08-026-10/+33
| | | | | | | | | | | | | | | | | | | | | | | Summary: Two types of stores are possible in pixel shaders: stores to memory that are explicitly requested at the API level, and stores that are an implementation detail of register spilling or lowering of arrays. For the first kind of store, we must ensure that helper pixels have no effect and hence WQM must be disabled. The second kind of store must always be executed, because the written value may be loaded again in a way that is relevant for helper pixels as well -- and there are no externally visible effects anyway. This is a candidate for the 3.9 release branch. Reviewers: arsenm, tstellarAMD, mareko Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: https://reviews.llvm.org/D22675 llvm-svn: 277504
* AMDGPU: Track physical registers in SIWholeQuadModeNicolai Haehnle2016-08-021-26/+53
| | | | | | | | | | | | | | | | | | | | Summary: There are cases where uniform branch conditions are computed in VGPRs, and we didn't correctly mark those as WQM. The stray change in basic-branch.ll is because invoking the LiveIntervals analysis leads to the detection of a dead register that would otherwise not be seen at -O0. This is a candidate for the 3.9 branch, as it fixes a possible hang. Reviewers: arsenm, tstellarAMD, mareko Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22673 llvm-svn: 277500
* [Hexagon] Prefer _io over _rr for 64-bit store with constant offsetKrzysztof Parzyszek2016-08-021-0/+13
| | | | | | | | | Identify patterns where the address is aligned to an 8-byte boundary, but both the base address and the constant offset are both proper multiples of 4. In such cases, extract Base+4 into a separate instruc- tion, and use S2_storerd_io, instead of using S4_storerd_rr. llvm-svn: 277497
* [Hexagon] Remove unused optionKrzysztof Parzyszek2016-08-021-7/+0
| | | | llvm-svn: 277496
* [Hexagon] Improvements to address mode checks in TargetLoweringKrzysztof Parzyszek2016-08-022-2/+39
| | | | | | | - Implement getOptimalMemOpType. - Check BaseOffset in isLegalAddressingMode. llvm-svn: 277494
* [MC] Fix Intel Operand assembly parsing for .set idsNirav Dave2016-08-021-116/+80
| | | | | | | | | | | | | | | | | Recommitting after fixing overaggressive fastpath return in parsing. Fix intel syntax special case identifier operands that refer to a constant (e.g. .set <ID> n) to be interpreted as immediate not memory in parsing. Associated commit to fix clang test commited shortly. Reviewers: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22585 llvm-svn: 277489
* [AArch64][GlobalISel] Mark basic binops/memops as legal.Ahmed Bougacha2016-08-021-1/+17
| | | | | | | | | | We currently use and test these, and select most of them. Mark them as legal even though we don't go through the full ir->asm flow yet. This doesn't currently have standalone tests, but the verifier will soon learn to check that the regbankselect/select tests are legal. llvm-svn: 277471
* [WebAssembly] Remove a README.txt entry that is now implemented.Dan Gohman2016-08-021-6/+0
| | | | llvm-svn: 277467
* [ARM] Improve smul* and smla* isel for Thumb2Sam Parker2016-08-023-25/+41
| | | | | | | | | | | | | | Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
* HexagonVectorPrint.cpp: Fix r277370. Don't use getInstrVecReg() in the ↵NAKAMURA Takumi2016-08-021-1/+2
| | | | | | expression of assert(). It has side effects. llvm-svn: 277448
* [mips] Update the P5600 scheduler for isComplete = 1Simon Dardis2016-08-023-32/+224
| | | | | | | | | | | These changes update the schedule model for the P5600 and includes the rest of the MSA and MIPS32R5 instruction sets. Reviewers: dsanders, vkalintris Differential Revision: https://reviews.llvm.org/D21835 llvm-svn: 277441
* [ARM] Some saturation instructions not DSP-onlyBernard Ogden2016-08-023-7/+7
| | | | | | | | | | | | | | | | | | | | | Summary: Commit 276701 requires that targets have the DSP extensions to use certain saturating instructions. This requires some corrections. For ARM ISA the instructions in question are available in all v6* architectures. For Thumb2, the instructions in question are available from v6T2. SSAT and USAT are part of the base architecture while SSAT16 and USAT16 require the DSP extensions. Reviewers: rengolin Subscribers: aemerson, rengolin, samparker, llvm-commits Differential Revision: https://reviews.llvm.org/D23010 llvm-svn: 277439
* [AVX512] Don't use i128 masked gather/scatter/load/store. Do more accurately ↵Igor Breger2016-08-021-3/+3
| | | | | | | | dataWidth check. Differential Revision: http://reviews.llvm.org/D23055 llvm-svn: 277435
* AArch64: Assert on branch displacement bitsMatt Arsenault2016-08-021-0/+7
| | | | llvm-svn: 277434
* AArch64: Consolidate branch inversion logicMatt Arsenault2016-08-021-20/+22
| | | | llvm-svn: 277431
* AArch64: BranchRelaxtion cleanupsMatt Arsenault2016-08-023-120/+178
| | | | | | Move some logic into TII. llvm-svn: 277430
* AArch64: Fix end iterator dereferenceMatt Arsenault2016-08-021-51/+57
| | | | | | | Not all blocks have terminators. I'm not sure how this wasn't crashing before. llvm-svn: 277427
* [AVX-512] Mark VADDPS/PD and VMULPS/PD as commutable. This necessitated ↵Craig Topper2016-08-021-27/+43
| | | | | | adding itineraries to all of the instructions that use the avx512_fp_binop_p class. llvm-svn: 277422
* [AVX-512] Use SSE_MUL_ITINS_S/SSE_DIV_ITINS_S for the scalar FMUL/FDIV ↵Craig Topper2016-08-021-2/+2
| | | | | | instructions to match SSE/AVX. llvm-svn: 277421
* [AVX-512] Correct ExeDomain for many AVX-512 instructions.Craig Topper2016-08-022-13/+32
| | | | llvm-svn: 277416
* Revert r276895 "[MC][X86] Fix Intel Operand assembly parsing for .set ids"Hans Wennborg2016-08-011-79/+115
| | | | | | This caused PR28805. Adding a regression test. llvm-svn: 277402
* [WebAssembly] Support CFI for WebAssembly targetDerek Schuff2016-08-014-3/+28
| | | | | | | | | | | | | | | Summary: This patch implements CFI for WebAssembly. It modifies the LowerTypeTest pass to pre-assign table indexes to functions that are called indirectly, and lowers type checks to test against the appropriate table indexes. It also modifies the WebAssembly backend to support a special ".indidx" assembly directive that propagates the table index assignments out to the linker. Patch by Dominic Chen Differential Revision: https://reviews.llvm.org/D21768 llvm-svn: 277398
* [WebAssembly] Add asm.js-style exception handling supportDerek Schuff2016-08-014-0/+477
| | | | | | | | | | | | | | | | | | Summary: This patch includes asm.js-style exception handling support for WebAssembly. The WebAssembly MVP does not have any support for unwinding or non-local control flow. In order to support C++ exceptions, emscripten currently uses JavaScript exceptions along with some support code (written in JavaScript) that is bundled by emscripten with the generated code. This scheme lowers exception-related instructions for wasm such that wasm modules can be compatible with emscripten's existing scheme and share the support code. Patch by Heejin Ahn Differential Revision: https://reviews.llvm.org/D22958 llvm-svn: 277391
* [Hexagon] Tidy up some code, NFC: reapply r277372 with a fixKrzysztof Parzyszek2016-08-012-192/+175
| | | | llvm-svn: 277383
* Revert r277372, it is causing buildbot failuresKrzysztof Parzyszek2016-08-012-173/+186
| | | | llvm-svn: 277374
* [Hexagon] Tidy up some code, NFCKrzysztof Parzyszek2016-08-012-186/+173
| | | | llvm-svn: 277372
* [Hexagon] Generate vector printing instructionsRon Lieberman2016-08-013-0/+188
| | | | llvm-svn: 277370
* [AArch64] Add support for Samsung Exynos M2 (NFC).Evandro Menezes2016-08-012-0/+7
| | | | llvm-svn: 277364
* Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFCKrzysztof Parzyszek2016-08-015-31/+31
| | | | | | There were a few cases introduced with the modulo scheduler. llvm-svn: 277358
* [Hexagon] Check for offset overflow when reserving scavenging slotsKrzysztof Parzyszek2016-08-012-2/+16
| | | | | | | | | Scavenging slots were only reserved when pseudo-instruction expansion in frame lowering created new virtual registers. It is possible to still need a scavenging slot even if no virtual registers were created, in cases where the stack is large enough to overflow instruction offsets. llvm-svn: 277355
* [mips][fastisel] Correct argument lowering for (f64, f64, i32) and similar.Daniel Sanders2016-08-011-29/+55
| | | | | | | | | | | | | | | Summary: Allocating an AFGR64 shadows two GPR32's instead of just one. This fixes an LNT regression detected by our internal buildbots. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D23012 llvm-svn: 277348
* [AMDGPU] refactor DS instruction definitions. NFC.Valery Pykhtin2016-08-017-608/+896
| | | | | | Differential revision: https://reviews.llvm.org/D22522 llvm-svn: 277344
* [X86] Use implicit masking of SHLD/SHRD shift double instructionsSimon Pilgrim2016-08-011-3/+16
| | | | | | Similar to the regular shift instructions, SHLD/SHRD only use the bottom bits of the shift value llvm-svn: 277341
* Fixed MSVC out of range shift warningSimon Pilgrim2016-08-011-1/+1
| | | | llvm-svn: 277333
* [AArch64] Return the correct size for TLSDESC_CALLSEQDiana Picus2016-08-011-0/+3
| | | | | | | | | | | | | | The branch relaxation pass is computing the wrong offsets because it assumes TLSDESC_CALLSEQ eats up 4 bytes, when in fact it is lowered to an instruction sequence taking up 16 bytes. This can become a problem in huge files with lots of TLS accesses, as it may slowly move branch targets out of the range computed by the branch relaxation pass. Fixes PR24234 https://llvm.org/bugs/show_bug.cgi?id=24234 Differential Revision: https://reviews.llvm.org/D22870 llvm-svn: 277331
* [AVX-512] Fix duplicate column in AVX512 execution dependency table that was ↵Craig Topper2016-08-011-18/+18
| | | | | | preventing VMOVDQU32/VMOVDQA32 from being recognized. Fix a bug in the code that stops execution dependency fix from turning operations on 32-bit integer element types into operations on 64-bit integer element types. llvm-svn: 277327
* [mips] Clang generates unaligned offset for MSA instruction st.dHrvoje Varga2016-08-016-49/+123
| | | | | | Differential Revision: https://reviews.llvm.org/D19475 llvm-svn: 277323
* [AArch64] Register passes so they can be run by llcDiana Picus2016-08-0115-110/+125
| | | | | | | | | | | | | | Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
* [AVX-512] Teach X86InstrInfo::getLargestLegalSuperClass to inflate to ↵Craig Topper2016-08-011-4/+26
| | | | | | | | FR32X/FR64X if AVX512 is supported and VR128X/VR256X if VLX is supported. Had to update a stack folding test to clobber the other 16 registers since this now made them get used instead of spilling. llvm-svn: 277321
* [AVX-512] Use FR32X/FR64X/VR128X/VR256X register classes in addRegisterClass ↵Craig Topper2016-08-011-15/+30
| | | | | | if AVX512(for FR32X/FR64) or VLX(for VR128X/VR256) is supported. This is a minimal requirement to be able to allocate all 32 registers. llvm-svn: 277319
* [X86] Move mask register handling into the main switch of ↵Craig Topper2016-08-011-22/+6
| | | | | | getLoadStoreRegOpcode. No functional change intended. llvm-svn: 277318
* [X86] Simplify code for determing GR or FR reg classes by querying for super ↵Craig Topper2016-07-311-49/+10
| | | | | | classes instead of manually listing individual classes. llvm-svn: 277306
* [AVX512] Always use EVEX encodings for 128/256-bit move instructions in ↵Craig Topper2016-07-311-24/+15
| | | | | | getLoadStoreRegOpcode if VLX is supported. llvm-svn: 277305
* [AVX512] Add VLX packed move instructions to the execution dependency fix ↵Craig Topper2016-07-311-5/+15
| | | | | | pass and update tests. llvm-svn: 277304
* [AVX512] Move FR32X/FR64X handling in getLoadStoreRegOpcode into the main ↵Craig Topper2016-07-311-15/+11
| | | | | | switch. No functional change intended. llvm-svn: 277303
* [AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the ↵Craig Topper2016-07-311-3/+1
| | | | | | regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned. llvm-svn: 277302
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