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* [CodeGenPrepare][NFC] Rename TargetTransformInfo::expandMemCmp -> ↵Clement Courbet2017-09-254-4/+4
| | | | | | | | | | | | | | | | TargetTransformInfo::enableMemCmpExpansion. Summary: Right now there are two functions with the same name, one does the work and the other one returns true if expansion is needed. Rename TargetTransformInfo::expandMemCmp to make it more consistent with other members of TargetTransformInfo. Remove the unused Instruction* parameter. Differential Revision: https://reviews.llvm.org/D38165 llvm-svn: 314096
* [X86] Make IFMA instructions during isel so we can fold broadcast loads.Craig Topper2017-09-245-21/+46
| | | | | | This required changing the ISD opcode for these instructions to have the commutable operands first and the addend last. This way tablegen can autogenerate the additional patterns for us. llvm-svn: 314083
* [X86] Add IFMA instructions to the load folding tables and make them ↵Craig Topper2017-09-242-1/+54
| | | | | | commutable for the multiply operands. llvm-svn: 314080
* Fix signed/unsigned warningSimon Pilgrim2017-09-241-1/+1
| | | | llvm-svn: 314078
* [X86][SSE] Add support for extending bool vectors bitcasted from scalarsSimon Pilgrim2017-09-241-0/+113
| | | | | | | | | | This patch acts as a reverse to combineBitcastvxi1 - bitcasting a scalar integer to a boolean vector and extending it 'in place' to the requested legal type. Currently this doesn't handle AVX512 at all - but the current mask register approach is lacking for some cases. Differential Revision: https://reviews.llvm.org/D35320 llvm-svn: 314076
* [PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGENemanja Ivanovic2017-09-241-0/+96
| | | | | | | | As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
* [AVX-512] Add pattern for selecting masked version of v8i32/v8f32 compare ↵Craig Topper2017-09-241-0/+17
| | | | | | | | instructions when VLX isn't available. We use a v16i32/v16f32 compare instead and truncate the result. We already did this for the unmasked version, but were missing the version with 'and'. llvm-svn: 314072
* [X86] Make sure we still mark the full register as implicitly defined when ↵Craig Topper2017-09-241-4/+10
| | | | | | | | we shrink 256/512 bit zeroing xors to 128-bit. Not sure if anything really cares, but this seems like the right thing to do. llvm-svn: 314071
* [AVR] Implement getCmpLibcallReturnType().Dylan McKay2017-09-241-0/+5
| | | | | | | | | This fixes the avr-rust issue (#75) with floating-point comparisons generating broken code. By default, LLVM assumes these comparisons return 32-bit values, but ours are 8-bit. Patch By Thomas Backman. llvm-svn: 314070
* [x86] reduce 64-bit mask constant to 32-bits by right shiftingSanjay Patel2017-09-231-13/+14
| | | | | | | | | | | | | | This is a follow-up from D38181 (r314023). We have to put 64-bit constants into a register using a separate instruction, so we should try harder to avoid that. From what I see, we're not likely to encounter this pattern in the DAG because the upstream setcc combines from this don't (usually?) produce this pattern. If we fix that, then this will become more relevant. Since the cost of handling this case is just loosening the predicate of the existing fold, we might as well do it now. llvm-svn: 314064
* [PowerPC] Eliminate compares - add i32 sext/zext handling for SETULT/SETUGTNemanja Ivanovic2017-09-231-3/+34
| | | | | | | | As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential revision. llvm-svn: 314062
* [PowerPC] Eliminate compares - add i32 sext/zext handling for SETULE/SETUGENemanja Ivanovic2017-09-232-1/+74
| | | | | | | | As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential revision. llvm-svn: 314060
* [X86] Move the getInsertVINSERTImmediate and getExtractVEXTRACTImmediate ↵Craig Topper2017-09-234-70/+22
| | | | | | | | helper functions over to X86ISelDAGToDAG.cpp Redefine them to call getI8Imm and return that directly. llvm-svn: 314059
* [X86] Remove is the isVINSERT*Index/isVEXTRACT*Index predicates from isel.Craig Topper2017-09-233-78/+8
| | | | | | The only insert_subvector/extract_subvector nodes that make it to isel are guaranteed to match. llvm-svn: 314058
* [PowerPC] Eliminate compares - add i32 sext/zext handling for SETLT/SETGTNemanja Ivanovic2017-09-231-0/+101
| | | | | | | | As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential revision. llvm-svn: 314055
* [X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038).Konstantin Belochapka2017-09-221-2/+5
| | | | | | | Fixed suboptimal encoding of instruction memory operand when assembler is used to select 32 bit fixup rather than 8 bit immediate for encoding memory offset value. Differential Revision: https://reviews.llvm.org/D38117 llvm-svn: 314044
* [PowerPC] Mark P9 scheduling model completeStefan Pintilie2017-09-224-266/+503
| | | | | | | | | | | | This patch just adds the missing information to the P9 scheduling model to allow the model to be marked as complete. The model has been verified against P9 documentation. The model was verified with utils/schedcover.py. Differential Revision: https://reviews.llvm.org/D35695 llvm-svn: 314026
* [x86] shiftRightAlgebraic -> shiftRightArithmetic; NFCSanjay Patel2017-09-221-2/+2
| | | | | | | x86 re-education camp is in session. The LLVM LangRef agrees with x86 too. The DAG nodes are undocumented and ambiguous as always. :) llvm-svn: 314024
* [x86] swap order of srl (and X, C1), C2 when it saves sizeSanjay Patel2017-09-221-0/+38
| | | | | | | | | | | | | | The (non-)obvious win comes from saving 3 bytes by using the 0x83 'and' opcode variant instead of 0x81. There are also better improvements based on known-bits that allow us to eliminate the mask entirely. As noted, this could be extended. There are potentially other wins from always shifting first, but doing that reveals a tangle of problems in other pattern matching. We do this transform generically in instcombine, but we often have icmp IR that doesn't match that pattern, so we must account for this in the backend. Differential Revision: https://reviews.llvm.org/D38181 llvm-svn: 314023
* [XRay] support conditional return on PPC.Tim Shen2017-09-223-56/+110
| | | | | | | | | | | | Summary: Conditional returns were not taken into consideration at all. Implement them by turning them into jumps and normal returns. This means there is a slightly higher performance penalty for conditional returns, but this is the best we can do, and it still disturbs little of the rest. Reviewers: dberris, echristo Subscribers: sanjoy, nemanjai, hiraditya, kbarton, llvm-commits Differential Revision: https://reviews.llvm.org/D38102 llvm-svn: 314005
* Check vector elements for equivalence in the HexagonVectorLoopCarriedReuse passPranav Bhandarkar2017-09-221-0/+15
| | | | | | | | | If the two instructions being compared for equivalence have corresponding operands that are integer constants, then check their values to determine equivalence. Patch by Suyog Sarda! llvm-svn: 313993
* [X86] Combining CMOVs with [ANY,SIGN,ZERO]_EXTEND for cases where CMOV has ↵Alexander Ivchenko2017-09-221-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | constant arguments Combine CMOV[i16]<-[SIGN,ZERO,ANY]_EXTEND to [i32,i64] into CMOV[i32,i64]. One example of where it is useful is: before (20 bytes) <foo>: test $0x1,%dil mov $0x307e,%ax mov $0xffff,%cx cmovne %ax,%cx movzwl %cx,%eax retq after (18 bytes) <foo>: test $0x1,%dil mov $0x307e,%ecx mov $0xffff,%eax cmovne %ecx,%eax retq Reviewers: craig.topper, aaboud, spatel, RKSimon, zvi Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36711 llvm-svn: 313982
* Remove the default clause from a fully-covering switchNemanja Ivanovic2017-09-221-4/+10
| | | | | | | to appease bots that use a compiler that warns about this and use -Werror. llvm-svn: 313980
* [ARM] Fix assembly and disassembly for VMRS/VMSRAndre Vieira2017-09-223-35/+71
| | | | | | | Reviewed by: t.p.northover Differential Revision: https://reviews.llvm.org/D36306 llvm-svn: 313979
* Recommit r310809 with a fix for the spill problemNemanja Ivanovic2017-09-221-51/+150
| | | | | | | | | | This patch re-commits the patch that was pulled out due to a problem it caused, but with a fix for the problem. The fix was reviewed separately by Eric Christopher and Hal Finkel. Differential Revision: https://reviews.llvm.org/D38054 llvm-svn: 313978
* [ARM] Add missing selection patterns for vnmlaSimon Pilgrim2017-09-221-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For the following function: double fn1(double d0, double d1, double d2) { double a = -d0 - d1 * d2; return a; } on ARM, LLVM generates code along the lines of vneg.f64 d0, d0 vmls.f64 d0, d1, d2 i.e., a negate and a multiply-subtract. The attached patch adds instruction selection patterns to allow it to generate the single instruction vnmla.f64 d0, d1, d2 (multiply-add with negation) instead, like GCC does. Committed on behalf of @gergo- (Gergö Barany) Differential Revision: https://reviews.llvm.org/D35911 llvm-svn: 313972
* [mips] clang-format MipsTargetMachine.cppAlexander Richardson2017-09-221-3/+3
| | | | | | This is my test commit as it only changes two lines llvm-svn: 313968
* [AVR] Remove the 'IsN64' argument to 'MCELFObjectWriter'Dylan McKay2017-09-221-1/+1
| | | | | | This has since been removed. llvm-svn: 313965
* bpf: initial 32-bit ALU encoding support in assemblerYonghong Song2017-09-222-46/+63
| | | | | | | | | | | | | | This patch adds instruction patterns for operations in BPF_ALU. After this, assembler could recognize some 32-bit ALU statement. For example, those listed int the unit test file. Separate MOV patterns are unnecessary as MOV is ALU operation that could reuse ALU encoding infrastructure, this patch removed those redundant patterns. Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 313961
* bpf: add 32bit register setYonghong Song2017-09-221-21/+32
| | | | | | | Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 313960
* bpf: refactor inst patterns with better inheritanceYonghong Song2017-09-221-111/+127
| | | | | | | | | | | | | | | | | Arithmetic and jump instructions, load and store instructions are sharing the same 8-bit code field encoding, A better instruction pattern implemention could be the following inheritance relationships, and each layer only encoding those fields which start to diverse from that layer. This avoids some redundant code. InstBPF -> TYPE_ALU_JMP -> ALU/JMP InstBPF -> TYPE_LD_ST -> Load/Store Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 313959
* bpf: refactor inst patterns with more mnemonicsYonghong Song2017-09-222-185/+189
| | | | | | | | | | | Currently, eBPF backend is using some constant directly in instruction patterns, This patch replace them with mnemonics and removed some unnecessary temparary variables. Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 313958
* AArch64: support SwiftCC properly on AAPCS64Saleem Abdulrasool2017-09-221-0/+3
| | | | | | | | | The previous SwiftCC support for AAPCS64 was partially correct. It setup swiftself parameters in the proper register but failed to setup swifterror in the correct register. This would break compilation of swift code for non-Darwin AAPCS64 conforming environments. llvm-svn: 313956
* HexagonVectorLoopCarriedReuse.cpp: Apply LLVM_ATTRIBUTE_UNUSED. ↵NAKAMURA Takumi2017-09-221-0/+2
| | | | | | [-Wunused-function] llvm-svn: 313947
* Reformat.NAKAMURA Takumi2017-09-221-2/+2
| | | | llvm-svn: 313946
* Fix unused variable warning.Richard Trieu2017-09-211-2/+1
| | | | | | | Move function call into debug macro to suppress unused variable warning in non-debug builds. llvm-svn: 313942
* Enable the reuse of values computed in a previous loop iteration.Pranav Bhandarkar2017-09-213-0/+588
| | | | | | | | | | This patch adds a pass that removes the computation of provably redundant expressions that have been computed earlier in a previous iteration. It relies on the use of PHIs to identify loop carried dependences. This is scalar replacement for vector types. llvm-svn: 313925
* [AArch64] Fix bug in store of vector 0 DAGCombine.Geoff Berry2017-09-211-5/+14
| | | | | | | | | | | | | | | | | Summary: Avoid using XZR/WZR directly as operands to split stores of zero vectors. Doing so can lead to the XZR/WZR being used by an instruction that doesn't allow it (e.g. add). Fixes bug 34674. Reviewers: t.p.northover, efriedma, MatzeB Subscribers: aemerson, rengolin, javed.absar, mcrosier, eraman, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D38146 llvm-svn: 313916
* [NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} ↵Artem Belevich2017-09-212-0/+66
| | | | | | | | instructions/intrinsics/builtins. Differential Revision: https://reviews.llvm.org/D38148 llvm-svn: 313898
* [Power9] Spill gprs to vector registers rather than stackZaara Syeda2017-09-214-1/+121
| | | | | | | | | | This patch updates register allocation to enable spilling gprs to volatile vector registers rather than the stack. It can be enabled for Power9 with option -ppc-enable-gpr-to-vsr-spills. Differential Revision: https://reviews.llvm.org/D34815 llvm-svn: 313886
* [mips] Do not pass redundant IsN64 flag to MCELFObjectTargetWriter. NFCSimon Atanasyan2017-09-211-5/+4
| | | | | | | | Now we pass the 'Is64_' flag to the MCELFObjectTargetWriter ctor iif when we make deal with N64 ABI. So it is redundant to pass additional 'IsN64' flag. llvm-svn: 313878
* [SystemZ] Improve optimizeCompareZero()Jonas Paulsson2017-09-211-7/+36
| | | | | | | | | | More conversions to load-and-test can be made with this patch by adding a forward search in optimizeCompareZero(). Review: Ulrich Weigand https://reviews.llvm.org/D38076 llvm-svn: 313877
* [mips] Fix relocation record format and ELF header for N32 ABISimon Atanasyan2017-09-215-10/+21
| | | | | | | | | | | | | | | The N32 ABI uses RELA relocation format, do not use 3-in-1 relocation's encoding, and uses ELFCLASS32. This change passes the `IsN32` flag to the `MCAsmBackend` to distinguish usage of N32 ABI. We still do not handle some cases like providing the `-target-abi=o32` command line option with the `mips64` target triple. That's why elf_header.s contains some "FIXME" strings. This case will be fixed in a separate patch. Differential revision: https://reviews.llvm.org/D37960 llvm-svn: 313873
* AMDGPU: Add option to stress callsMatt Arsenault2017-09-211-3/+13
| | | | | | | This inverts the behavior of the AlwaysInline pass to mark every function not already marked alwaysinline as noinline. llvm-svn: 313865
* [X86] Remove execute permissions from a couple files.Craig Topper2017-09-212-0/+0
| | | | llvm-svn: 313863
* [X86] Remove windows line endings.Craig Topper2017-09-211-919/+919
| | | | llvm-svn: 313862
* [X86] Remove unused tablegen class.Craig Topper2017-09-211-7/+0
| | | | llvm-svn: 313861
* AMDGPU: Fix crash on immediate operandMatt Arsenault2017-09-211-1/+5
| | | | | | | | We can have a v_mac with an immediate src0. We can still fold if it's an inline immediate, otherwise it already uses the constant bus. llvm-svn: 313852
* [X86] Replace a condition that can never be true with an assert.Craig Topper2017-09-211-2/+2
| | | | llvm-svn: 313848
* [ARM] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-09-2017-233/+456
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 313823
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