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* [Hexagon] Converting multiply and accumulate with immediate intrinsics to ↵Colin LeMahieu2015-01-211-0/+21
| | | | | | patterns. llvm-svn: 226681
* [X86] Declare SSE4.1/AVX2 vector extloads covered by PMOV[SZ]X legal.Ahmed Bougacha2015-01-212-9/+70
| | | | | | | | | | | | | | | | | | Now that we can fully specify extload legality, we can declare them legal for the PMOVSX/PMOVZX instructions. This for instance enables a DAGCombine to fire on code such as (and (<zextload-equivalent> ...), <redundant mask>) to turn it into: (zextload ...) as seen in the testcase changes. There is one regression, in widen_load-2.ll: we're no longer able to do store-to-load forwarding with illegal extload memory types. This will be addressed separately. Differential Revision: http://reviews.llvm.org/D6533 llvm-svn: 226676
* AArch64: add backend option to reserve x18 (platform register)Tim Northover2015-01-211-3/+7
| | | | | | | | | AAPCS64 says that it's up to the platform to specify whether x18 is reserved, and a first step on that way is to add a flag controlling it. From: Andrew Turner <andrew@fubar.geek.nz> llvm-svn: 226664
* [x32] Fast ISel should use LEA64_32r instead of LEA32r to adjust addresses ↵Michael Kuperstein2015-01-211-2/+8
| | | | | | in x32 mode. llvm-svn: 226661
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-2111-1/+153
| | | | | | | | | | | | | | Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226657
* [mips][microMIPS] Implement ADDIUPC instructionJozef Kolek2015-01-216-0/+56
| | | | | | Differential Revision: http://reviews.llvm.org/D6582 llvm-svn: 226656
* [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 ↵Vladimir Medic2015-01-212-0/+23
| | | | | | instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. llvm-svn: 226652
* [x86] Remove some unnecessary and slightly confusing typecasts from some ↵Craig Topper2015-01-211-4/+4
| | | | | | patterns. I think it actually went i32->iPtr->i32 in some of these cases. llvm-svn: 226647
* [X86] Convert all the i8imm used by AVX512 and MMX instructions to u8imm.Craig Topper2015-01-212-27/+27
| | | | llvm-svn: 226646
* [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm.Craig Topper2015-01-213-77/+66
| | | | | | This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate. llvm-svn: 226645
* [x86] Add assembly parser bounds checking to the immediate value for ↵Craig Topper2015-01-215-14/+40
| | | | | | cmpss/cmpsd/cmpps/cmppd. llvm-svn: 226642
* [Hexagon] Adding intrinsics for doubleword ALU operations.Colin LeMahieu2015-01-201-0/+19
| | | | llvm-svn: 226606
* R600/SI: Add subtarget feature to enable VGPR spilling for all shader typesTom Stellard2015-01-209-11/+36
| | | | | | | This is disabled by default, but can be enabled with the subtarget feature: 'vgpr-spilling' llvm-svn: 226597
* R600/SI: Fix simple-loop.ll testTom Stellard2015-01-202-5/+9
| | | | llvm-svn: 226596
* Reverted revision 226577.Jozef Kolek2015-01-2011-152/+1
| | | | llvm-svn: 226595
* R600/SI: Remove stray debugging code from r226586Tom Stellard2015-01-201-2/+0
| | | | llvm-svn: 226591
* R600/SI: Use external symbols for scratch bufferTom Stellard2015-01-209-82/+92
| | | | | | | | We were passing the scratch buffer address to the shaders via user sgprs, but now we use external symbols and have the driver patch the shader using reloc information. llvm-svn: 226586
* R600/SI: Add kill flag when copying scratch offset to a registerTom Stellard2015-01-201-1/+1
| | | | | | | This allows us to re-use the same register for the scratch offset when accessing large private arrays. llvm-svn: 226585
* R600/SI: Don't store scratch buffer frame index in MUBUF offset fieldTom Stellard2015-01-201-16/+0
| | | | | | | | We don't have a good way of legalizing this if the frame index offset is more than the 12-bits, which is size of MUBUF's offset field, so now we store the frame index in the vaddr field. llvm-svn: 226584
* R600/SI: Update SIInstrInfo:verifyInstruction() after r225662Tom Stellard2015-01-201-6/+12
| | | | | | | Now that we have our own custom register operand types, we need to handle them in the verifiier. llvm-svn: 226583
* Silencing a -Wunused-variable warning in non-asserts builds; NFC.Aaron Ballman2015-01-201-3/+2
| | | | llvm-svn: 226581
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-2011-1/+153
| | | | | | | | | | | | | | Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226577
* [mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132Kai Nacke2015-01-202-0/+83
| | | | | | | | | This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
* [x86] Add some mayLoad/hasSideEffects flags. Remove one that was already ↵Craig Topper2015-01-202-3/+7
| | | | | | covered by a pattern. llvm-svn: 226562
* [X86][AVX] Missing AVX1 memory folding float instructionsSimon Pilgrim2015-01-191-2/+54
| | | | | | | | | | Now that we can create much more exhaustive X86 memory folding tests, this patch adds the missing AVX1/F16C floating point instruction stack foldings we can easily test for including the scalar intrinsics (add, div, max, min, mul, sub), conversions float/int to double, half precision conversions, rounding, dot product and bit test. The patch also adds a couple of obviously missing SSE instructions (more to follow once we have full SSE testing). Now that scalar folding is working it broke a very old test (2006-10-07-ScalarSSEMiscompile.ll) - this test appears to make no sense as its trying to ensure that a scalar subtraction isn't folded as it 'would zero the top elts of the loaded vector' - this test just appears to be wrong to me. Differential Revision: http://reviews.llvm.org/D7055 llvm-svn: 226513
* Add r224985 back with fixes.Rafael Espindola2015-01-197-182/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fixes are to note that AArch64 has additional restrictions on when local relocations can be used. In particular, ld64 requires that relocations to cstring/cfstrings use linker visible symbols. Original message: In an assembly expression like bar: .long L0 + 1 the intended semantics is that bar will contain a pointer one byte past L0. In sections that are merged by content (strings, 4 byte constants, etc), a single position in the section doesn't give the linker enough information. For example, it would not be able to tell a relocation must point to the end of a string, since that would look just like the start of the next. The solution used in ELF to use relocation with symbols if there is a non-zero addend. In MachO before this patch we would just keep all symbols in some sections. This would miss some cases (only cstrings on x86_64 were implemented) and was inefficient since most relocations have an addend of 0 and can be represented without the symbol. This patch implements the non-zero addend logic for MachO too. llvm-svn: 226503
* [Hexagon] Updating muxir/ri/ii intrinsics. Setting predicate registers as ↵Colin LeMahieu2015-01-193-101/+93
| | | | | | compatible with i32 rather than doing custom type conversion. llvm-svn: 226500
* [Hexagon] Converting intrinsics combine imm/imm, simple shifts and extends.Colin LeMahieu2015-01-191-0/+42
| | | | llvm-svn: 226483
* [Hexagon] Converting remaining ALU32/ALU intrinsics.Colin LeMahieu2015-01-193-29/+38
| | | | llvm-svn: 226480
* [Hexagon] Converting ALU32/ALU intrinsics to new patterns.Colin LeMahieu2015-01-191-30/+22
| | | | llvm-svn: 226478
* [AArch64] Implement GHC calling conventionGreg Fitzgerald2015-01-195-1/+62
| | | | | | | | | | Original patch by Luke Iannini. Minor improvements and test added by Erik de Castro Lopo. Differential Revision: http://reviews.llvm.org/D6877 From: Erik de Castro Lopo <erikd@mega-nerd.com> llvm-svn: 226473
* [Hexagon] Converting halfword to double accumulating multiply intrinsics.Colin LeMahieu2015-01-191-141/+50
| | | | llvm-svn: 226472
* [ARM] SSAT/USAT with an 'asr #32' shift should result in an undefined ↵Bradley Smith2015-01-191-1/+1
| | | | | | encoding rather than unpredictable llvm-svn: 226469
* [ARM] Fixup sign extend instruction availability w.r.t. DSP extensionBradley Smith2015-01-191-22/+33
| | | | llvm-svn: 226468
* Bring r226038 back.Rafael Espindola2015-01-191-2/+0
| | | | | | | | | | | | | | | | No change in this commit, but clang was changed to also produce trivial comdats when needed. Original message: Don't create new comdats in CodeGen. This patch stops the implicit creation of comdats during codegen. Clang now sets the comdat explicitly when it is required. With this patch clang and gcc now produce the same result in pr19848. llvm-svn: 226467
* [PM] Replace the Pass argument to SplitEdge with specific analyses usedChandler Carruth2015-01-191-1/+1
| | | | | | | | | | | | | | | and updated. This may appear to remove handling for things like alias analysis when splitting critical edges here, but in fact no callers of SplitEdge relied on this. Similarly, all of them wanted to preserve LCSSA if there was any update of the loop info. That makes the interface much simpler. With this, all of BasicBlockUtils.h is free of Pass arguments and prepared for the new pass manager. This is tho majority of utilities that relied on pass arguments. llvm-svn: 226459
* [PowerPC] Minor correction to r226432Hal Finkel2015-01-191-2/+1
| | | | | | | | | | We don't need to exclude patchpoints from the implicit r2 dependence in FastISel because it is added as an implicit operand and, thus, should not confuse that StackMap code. By inspection / no test case. llvm-svn: 226434
* [PowerPC] Add r2 as an operand for all calls under both PPC64 ELF V1 and V2Hal Finkel2015-01-192-5/+18
| | | | | | | | | | | Our PPC64 ELF V2 call lowering logic added r2 as an operand to all direct call instructions in order to represent the dependency on the TOC base pointer value. Restricting this to ELF V2, however, does not seem to make sense: calls under ELF V1 have the same dependence, and indirect calls have an r2 dependence just as direct ones. Make sure the dependence is noted for all calls under both ELF V1 and ELF V2. llvm-svn: 226432
* [x86] Change AVX512 intrinsics to take a 8-bit immediate for the comparision ↵Craig Topper2015-01-192-8/+4
| | | | | | kind instead of a 32-bit immediate. This better aligns with the emitted instruction. It also matches SSE and AVX1 equivalents. Also add auto upgrade support. llvm-svn: 226430
* unique_ptrify the RelInfo parameter to TargetRegistry::createMCSymbolizerDavid Blaikie2015-01-181-7/+5
| | | | llvm-svn: 226416
* std::unique_ptrify the MCStreamer argument to createAsmPrinterDavid Blaikie2015-01-1815-44/+65
| | | | llvm-svn: 226414
* [PowerPC] Don't hard-code R2 as register when processing TOC relocationsHal Finkel2015-01-181-3/+3
| | | | | | | | | | | Instructions that have high-order TOC relocations always carry R2 as their base register, so it does not matter whether we take the register from the instruction or just hard-code it in PPCAsmPrinter. In the future, however, we might want to apply these relocations to instructions using a different register, so taking the register from the instruction is a better thing to do. No change in functionality here, however. llvm-svn: 226403
* [PowerPC] Add some FIXMEs for fastcc and FPR <-> GPR movesHal Finkel2015-01-181-0/+6
| | | | | | | So we don't forget, once we support FPR <-> GPR moves on the P8, we'll likely want to re-visit this part of the calling convention. llvm-svn: 226401
* [PowerPC] Initial PPC64 calling-convention changes for fastccHal Finkel2015-01-182-63/+161
| | | | | | | | | | | | | | | | | The default calling convention specified by the PPC64 ELF (V1 and V2) ABI is designed to work with both prototyped and non-prototyped/varargs functions. As a result, GPRs and stack space are allocated for every argument, even those that are passed in floating-point or vector registers. GlobalOpt::OptimizeFunctions will transform local non-varargs functions (that do not have their address taken) to use the 'fast' calling convention. When functions are using the 'fast' calling convention, don't allocate GPRs for arguments passed in other types of registers, and don't allocate stack space for arguments passed in registers. Other changes for the fast calling convention may be added in the future. llvm-svn: 226399
* [PM] Split the LoopInfo object apart from the legacy pass, creatingChandler Carruth2015-01-171-4/+4
| | | | | | | | | | a LoopInfoWrapperPass to wire the object up to the legacy pass manager. This switches all the clients of LoopInfo over and paves the way to port LoopInfo to the new pass manager. No functionality change is intended with this iteration. llvm-svn: 226373
* [PowerPC] Don't list R11 as a patchpoint scratch registerHal Finkel2015-01-171-9/+1
| | | | | | | | | | R11's status is the same under both the PPC64 ELF V1 and V2 ABIs: it is reserved for use as an "environment pointer" for compilation models that require such a thing. We don't, we also don't need a second scratch register, and because we support only "local" patchpoint call targets, we might as well let R11 be used for anyregcc patchpoints. llvm-svn: 226369
* [Hexagon] Converting halfword to doubleword multiply intrinsics.Colin LeMahieu2015-01-161-37/+33
| | | | llvm-svn: 226326
* [Hexagon] Converting accumulating halfword multiply intrinsics to patterns.Colin LeMahieu2015-01-161-90/+65
| | | | llvm-svn: 226324
* [Hexagon] Beginning converting intrinsics to patterns instead of duplicated ↵Colin LeMahieu2015-01-161-71/+54
| | | | | | definitions. Converting halfword multiply intrinsics. llvm-svn: 226318
* [Hexagon] Fix 226309, replacement atomic store patterns didn't actually ↵Colin LeMahieu2015-01-161-0/+17
| | | | | | exist, added new versions. llvm-svn: 226315
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