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* Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,Duncan Sands2010-10-311-16/+1
| | | | | | | which has the same logic specified in the CallingConv TD file. This brings FastISel in line with the standard X86 ISel. llvm-svn: 117855
* Make sure we have a legal type (and simple) before continuing.Eric Christopher2010-10-301-1/+4
| | | | llvm-svn: 117848
* Resolve a terrible hack in tblgen: instead of hardcodingChris Lattner2010-10-301-2/+2
| | | | | | | "In32BitMode" and "In64BitMode" into tblgen, allow any predicate that inherits from AssemblerPredicate. llvm-svn: 117831
* Implement (and document!) support for MnemonicAlias's to have Requires Chris Lattner2010-10-302-14/+20
| | | | | | | | | | | directives, allowing things like this: def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; Move the rest of the X86 MnemonicAliases over to the .td file. llvm-svn: 117830
* really zap alias.Chris Lattner2010-10-301-1/+0
| | | | llvm-svn: 117824
* move fcompi alias to .td file and zap some useless code.Chris Lattner2010-10-302-11/+1
| | | | llvm-svn: 117823
* move rep aliases to td fileChris Lattner2010-10-302-5/+7
| | | | llvm-svn: 117822
* move sal aliases to .td file.Chris Lattner2010-10-302-5/+5
| | | | llvm-svn: 117821
* fix an encoding mismatch where "sal %eax, 1" was not using the short encodingChris Lattner2010-10-301-1/+1
| | | | | | for shl. Caught by inspection. llvm-svn: 117820
* move a bunch more aliases from .cpp -> .td file.Chris Lattner2010-10-302-22/+27
| | | | llvm-svn: 117819
* move cmov aliases to .td file.Chris Lattner2010-10-302-49/+25
| | | | llvm-svn: 117818
* move setcc and jcc aliases from .cpp to .tdChris Lattner2010-10-302-14/+28
| | | | llvm-svn: 117817
* move some code.Chris Lattner2010-10-301-33/+35
| | | | llvm-svn: 117816
* implement (and document!) the first kind of MC assembler alias, which Chris Lattner2010-10-302-15/+23
| | | | | | | just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. llvm-svn: 117815
* Add FIXME.Jim Grosbach2010-10-301-0/+2
| | | | llvm-svn: 117787
* Clean up comments.Jim Grosbach2010-10-301-1/+5
| | | | llvm-svn: 117785
* Tidy up.Jim Grosbach2010-10-301-1/+1
| | | | llvm-svn: 117782
* stay out of the reserved namespaceChris Lattner2010-10-301-6/+6
| | | | llvm-svn: 117773
* simplify this code.Chris Lattner2010-10-301-8/+4
| | | | llvm-svn: 117771
* split MaybeParseRegister into its two logical uses, eliminating malloc+free ↵Chris Lattner2010-10-301-35/+38
| | | | | | traffic. llvm-svn: 117769
* Avoid re-evaluating MI.getNumOperands() every iteration of the loop.Jim Grosbach2010-10-301-1/+1
| | | | llvm-svn: 117766
* Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson2010-10-305-131/+61
| | | | | | | | | | | | | | | | | | | There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
* Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach2010-10-304-0/+23
| | | | llvm-svn: 117753
* Some instructions end with an "ls" prefix, but it doesn't indicate that they areBill Wendling2010-10-291-3/+9
| | | | | | conditional. Check for those instructions explicitly. llvm-svn: 117747
* Remove hard tab characters.Jim Grosbach2010-10-291-3/+3
| | | | llvm-svn: 117742
* 80 column fix.Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117741
* trailing whitespaceJim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117740
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-293-3/+3
| | | | | | encoder functions. llvm-svn: 117738
* Fix fpscr <-> GPR latency info.Evan Cheng2010-10-293-4/+12
| | | | llvm-svn: 117737
* add FIXMEJim Grosbach2010-10-291-0/+5
| | | | llvm-svn: 117718
* Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it inJim Grosbach2010-10-294-45/+32
| | | | | | the ARMExpandPseudos pass rather than during the asm lowering. llvm-svn: 117714
* Handle comparison values we already have - this fixes the consumer-typesetEric Christopher2010-10-291-4/+65
| | | | | | failure for llvm-gcc on arm fast isel. llvm-svn: 117710
* ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need toJim Grosbach2010-10-291-55/+0
| | | | | | handle it in the asm lowering. llvm-svn: 117707
* Fix typo.Jim Grosbach2010-10-291-1/+1
| | | | llvm-svn: 117703
* ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj ↵Jim Grosbach2010-10-292-20/+25
| | | | | | pseudos and a FIXME for TLS. llvm-svn: 117702
* ARM mode LDREX*/STREX* binary encodings.Jim Grosbach2010-10-292-18/+28
| | | | llvm-svn: 117695
* Encoding information for ARM conditional move instructions.Jim Grosbach2010-10-291-19/+35
| | | | llvm-svn: 117687
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-291-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | operand and one of them has a single use that is a live out copy, favor the one that is live out. Otherwise it will be difficult to eliminate the copy if the instruction is a loop induction variable update. e.g. BB: sub r1, r3, #1 str r0, [r2, r3] mov r3, r1 cmp bne BB => BB: str r0, [r2, r3] sub r3, r3, #1 cmp bne BB This fixed the recent 256.bzip2 regression. llvm-svn: 117675
* - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.Evan Cheng2010-10-291-3/+7
| | | | | | - Compute CopyToReg use operand latency correctly. llvm-svn: 117674
* Handle ARM addrmode5 instructions with an offset.Jim Grosbach2010-10-291-9/+24
| | | | llvm-svn: 117672
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-2917-24/+393
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* Revert 117660. Apparently it's not as trivial as that...Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117663
* ARM addrmode5 instructions have neither writeback nor post-indexed modes.Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117660
* Trailing whitespace.Jim Grosbach2010-10-291-30/+30
| | | | llvm-svn: 117651
* ARMAsmParser: Plug a memory leak.Benjamin Kramer2010-10-291-2/+3
| | | | llvm-svn: 117648
* Add an unreachable to silence warning - the switch is actuallyEric Christopher2010-10-291-0/+2
| | | | | | fully enumerated. llvm-svn: 117647
* add simple support for addrmode5 operands, allowingChris Lattner2010-10-292-10/+31
| | | | | | | vldr.64 to work. I have no idea if this is fully right, but it is in the right direction. llvm-svn: 117626
* give better error diagnostics, for example:Chris Lattner2010-10-281-5/+20
| | | | | | | | | | | | | | t.s:1:14: error: invalid operand for instruction vldr.64 d17, [r0] ^ instead of: t.s:1:1: error: unrecognized instruction vldr.64 d17, [r0] ^ llvm-svn: 117611
* hook up getOpcodeName for ARM so that "llc -show-mc-inst" includesChris Lattner2010-10-282-0/+9
| | | | | | | | | | | | | | | the opcode string in the inst dump, e.g.: vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec] @ <MCInst #989 VMOVRRD @ <MCOperand Reg:68> @ <MCOperand Reg:69> @ <MCOperand Reg:19> @ <MCOperand Imm:14> @ <MCOperand Reg:0>> The "VMOVRRD" is new. llvm-svn: 117609
* move a method out of line.Chris Lattner2010-10-281-13/+20
| | | | llvm-svn: 117605
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