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* Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,Evan Cheng2011-07-2215-293/+236
| | | | | | InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC. llvm-svn: 135812
* Fix PR10422 by adding the necessary AVX UCOMISD memory versions toBruno Cardoso Lopes2011-07-221-2/+8
| | | | | | load folding logic llvm-svn: 135801
* ARM assembly parsing and encoding of SMLAL instruction.Jim Grosbach2011-07-221-1/+1
| | | | | | Fix parsing of carry-setting variant SMLALS and add tests. llvm-svn: 135797
* ARM encoding and assembly parsing of SMLAD{X} instructions.Jim Grosbach2011-07-221-6/+8
| | | | | | Fix encoding of destination register. Add tests. llvm-svn: 135796
* Add v8f32->v8i32 bitcast. Fixes PR10440Bruno Cardoso Lopes2011-07-221-0/+1
| | | | llvm-svn: 135794
* Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64Rafael Espindola2011-07-221-9/+5
| | | | | | too. Patch by Jeff Muizelaar. llvm-svn: 135789
* Fix x86's XALUO lowering to return its replacement values insteadDan Gohman2011-07-221-4/+2
| | | | | | | of doing the RAUW calls for the overflow value itself. This makes it more consistent with how the rest of LegalizeDAG works. llvm-svn: 135788
* Fix test failures caused by my so_reg refactoring.Owen Anderson2011-07-221-2/+2
| | | | llvm-svn: 135785
* ARM assembly parsing and encoding for SMC instruction.Jim Grosbach2011-07-222-3/+3
| | | | llvm-svn: 135782
* Clean up a few more comments.Jim Grosbach2011-07-221-5/+5
| | | | | | | These instruction definitions are for the assembler, too, not just the disassembler. llvm-svn: 135781
* Tidy up.Jim Grosbach2011-07-221-2/+1
| | | | llvm-svn: 135779
* Thumb assembly support for SETEND instruction.Jim Grosbach2011-07-222-16/+11
| | | | llvm-svn: 135778
* Tidy up.Jim Grosbach2011-07-221-1/+1
| | | | llvm-svn: 135777
* ARM assembly parsing and encoding for SETEND instruction.Jim Grosbach2011-07-222-6/+52
| | | | | | | Add parsing and diagnostics for malformed inputs. Tests for diagnostics and for correct encodings. llvm-svn: 135776
* Tidy up.Jim Grosbach2011-07-221-6/+2
| | | | llvm-svn: 135771
* Move TargetRegistry.cpp from lib/Support to lib/Target where it belongs.Chandler Carruth2011-07-222-0/+123
| | | | | | | | | | | | | | The header file was already properly located. The previous need for it in Support had to do with the version string printing which was fixed in r135757. Also update build dependencies where libraries that needed the functionality of the Target library (in the form of the TargetRegistry) were picking it up via Support. This is pretty pervasive, essentially every TargetInfo library (ARMInfo, etc) uses TargetRegistry, making it depend on Target. All of these were previously just sneaking by. llvm-svn: 135760
* GCC complains about the angle of this line.Benjamin Kramer2011-07-221-1/+1
| | | | | | Remove the escaped newline. llvm-svn: 135739
* Remove the 128-bit special handling from SCALAR_TO_VECTOR. This isn'tBruno Cardoso Lopes2011-07-221-18/+0
| | | | | | | | the way to go. Doing this here will prevent several node matches later, and would have to force looking all the way through several VINSERTF128/VEXTRACTF128 chains to optimize simple things. llvm-svn: 135730
* -Inspected a AVX code block added by someone in early Feb. This was never usedBruno Cardoso Lopes2011-07-222-76/+25
| | | | | | | | | | | | | | | | and was actually very wrong, fix it and make it simpler. Also remove the ConcatVectors function, which is unused now. - Fix a introduction of useless nodes in r126664 and r126264. The VUNPCKL* should never be introduced cause we don't want duplicate nodes for 128 AVX and non-AVX modes, the actual instruction difference only exists during isel, but not for target specific DAG nodes. We only introduce V* target nodes when there is no 128-bit version already there. - Fix a fragile test and make it more useful. llvm-svn: 135729
* Add a DAGCombine for transforming 128->256 casts into a simpleBruno Cardoso Lopes2011-07-221-7/+61
| | | | | | vxorps + vinsertf128 pair of instructions llvm-svn: 135727
* Introduce a new function to lower 256-bit vectors which are notBruno Cardoso Lopes2011-07-221-0/+14
| | | | | | | direclty supported and should be promoted and handled by smaller shuffles llvm-svn: 135726
* Rename function to be more specific and be more strict about its usageBruno Cardoso Lopes2011-07-221-6/+9
| | | | llvm-svn: 135725
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-2111-98/+258
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* ARM Asm parser range checking for [0,31] immediates.Jim Grosbach2011-07-212-0/+14
| | | | llvm-svn: 135719
* ARM assembly parsing support for RSC instruction.Jim Grosbach2011-07-211-0/+13
| | | | | | | Add two-operand instruction aliases. Add parsing and encoding tests for variants of the instruction. llvm-svn: 135713
* ARM assembly parsing support for RSB instruction.Jim Grosbach2011-07-211-0/+14
| | | | | | | Add two-operand instruction aliases. Add parsing and encoding tests for variants of the instruction. llvm-svn: 135712
* Tidy up.Jim Grosbach2011-07-211-2/+0
| | | | llvm-svn: 135706
* Update generated CPP code with the new API on CallInst::Create and ↵Nicolas Geoffray2011-07-211-5/+2
| | | | | | ConstantExpr::getGetElementPtr. llvm-svn: 135704
* ARM assembly parsing POP/PUSH mnemonics.Jim Grosbach2011-07-211-0/+6
| | | | | | | | Aliases for LDM/STM. The single-register versions should encode to LDR/STR with writeback, but we don't (yet) get that correct. Neither does Darwin's system assembler, though, so that's not a deal-breaker of a limitation. llvm-svn: 135702
* Fix CMake buildOscar Fuentes2011-07-211-0/+1
| | | | llvm-svn: 135698
* Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, ↵Owen Anderson2011-07-216-66/+329
| | | | | | allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
* ARM assembly parsing and encoding for PKHBT and PKHTB instructions.Jim Grosbach2011-07-213-0/+100
| | | | llvm-svn: 135682
* Added the infrastructute necessary for MIPS JIT support. Patch by VladimirBruno Cardoso Lopes2011-07-219-3/+519
| | | | | | | | Stefanovic. I removed the part that actually emits the instructions cause I want that to get in better shape first and in incremental steps. This also makes it easier to review the upcoming parts. llvm-svn: 135678
* Convert ConstantExpr::getGetElementPtr andJay Foad2011-07-211-1/+1
| | | | | | ConstantExpr::getInBoundsGetElementPtr to use ArrayRef. llvm-svn: 135673
* - Register v16i16 as valid VR256 register classBruno Cardoso Lopes2011-07-212-19/+22
| | | | | | | | - Add more bitcasts for v16i16 - Since 135661 and 135662 already added the splat logic, just add one more splat test for v16i16 llvm-svn: 135663
* Add support for 256-bit versions of VPERMIL instruction. This is a newBruno Cardoso Lopes2011-07-217-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instruction introduced in AVX, which can operate on 128 and 256-bit vectors. It considers a 256-bit vector as two independent 128-bit lanes. It can permute any 32 or 64 elements inside a lane, and restricts the second lane to have the same permutation of the first one. With the improved splat support introduced early today, adding codegen for this instruction enable more efficient 256-bit code: Instead of: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vextractf128 $1, %ymm0, %xmm1 shufps $1, %xmm1, %xmm1 movss %xmm1, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm1, 20(%rsp) movss %xmm1, 16(%rsp) vextractf128 $0, %ymm0, %xmm0 shufps $1, %xmm0, %xmm0 movss %xmm0, 12(%rsp) movss %xmm0, 8(%rsp) movss %xmm0, 4(%rsp) movss %xmm0, (%rsp) vmovaps (%rsp), %ymm0 We get: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vpermilps $85, %ymm0, %ymm0 llvm-svn: 135662
* Improve splat promotion to handle AVX types: v32i8 and v16i16. AlsoBruno Cardoso Lopes2011-07-211-24/+87
| | | | | | | | | refactor the code and add a bunch of comments. The final shuffle emitted by handling 256-bit types is suitable for the VPERM shuffle instruction which is going to be introduced in a next commit (with a testcase which cover this commit) llvm-svn: 135661
* Add aditional patterns for vextractf128 instructionBruno Cardoso Lopes2011-07-211-0/+8
| | | | llvm-svn: 135660
* Add aditional patterns for vinsertf128 instructionBruno Cardoso Lopes2011-07-211-0/+8
| | | | llvm-svn: 135659
* Add v16i16 type to VR256 classBruno Cardoso Lopes2011-07-211-2/+2
| | | | llvm-svn: 135658
* Move code around. No functionality changesBruno Cardoso Lopes2011-07-211-65/+78
| | | | llvm-svn: 135657
* Tidy up codeBruno Cardoso Lopes2011-07-211-15/+5
| | | | llvm-svn: 135656
* Mark instructions which are part of the frame setup with the ↵Bill Wendling2011-07-211-9/+20
| | | | | | MachineInstr::FrameSetup flag. llvm-svn: 135645
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-2029-192/+200
| | | | | | ARM MC code from target. llvm-svn: 135636
* Remove unused function.Bill Wendling2011-07-201-64/+0
| | | | llvm-svn: 135635
* Remove the now defunct getCompactUnwindEncoding method from the frame ↵Bill Wendling2011-07-202-118/+0
| | | | | | lowering code. llvm-svn: 135634
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-206-18/+39
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* Tidy up a bit.Jim Grosbach2011-07-203-12/+7
| | | | | | | Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename them to be a bit more descriptive that they're for the PKH instructions. llvm-svn: 135617
* ARM: Tidy up representation of PKH instruction.Jim Grosbach2011-07-205-37/+35
| | | | | | | | | The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't be also encoded as part of the shift value immediate. Otherwise we're able to represent invalid instructions, plus it needlessly complicates the representation. Preparatory work for asm parsing of these instructions. llvm-svn: 135616
* Fix cmake again :)Benjamin Kramer2011-07-201-1/+0
| | | | llvm-svn: 135613
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