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* GlobalISel: support selecting G_GEP instructions.Tim Northover2016-10-101-1/+3
| | | | | | They're basically just an alias for G_ADD on AArch64. llvm-svn: 283807
* GlobalISel: support selecting constants on AArch64.Tim Northover2016-10-101-0/+10
| | | | llvm-svn: 283806
* [ARM] Fix invalid VLDM/VSTM access when targeting Big Endian with NEONAlexandros Lamprineas2016-10-101-2/+12
| | | | | | | | | | | | | | | The instructions VLDM/VSTM can only access word-aligned memory locations and produce alignment fault if the condition is not met. The compiler currently generates VLDM/VSTM for v2f64 load/store regardless the alignment of the memory access. Instead, if a v2f64 load/store is not word-aligned, the compiler should generate VLD1/VST1. For each non double-word-aligned VLD1/VST1, a VREV instruction should be generated when targeting Big Endian. Differential Revision: https://reviews.llvm.org/D25281 llvm-svn: 283763
* [X86] Prefer rotate by 1 over rotate by immZvi Rackover2016-10-101-4/+4
| | | | | | | | | | | | | Summary: Rotate by 1 is translated to 1 micro-op, while rotate with imm8 is translated to 2 micro-ops. Fixes pr30644. Reviewers: delena, igorb, craig.topper, spatel, RKSimon Differential Revision: https://reviews.llvm.org/D25399 llvm-svn: 283758
* This pass, fixing an erratum in some LEON 2 processors ensures that the SDIV ↵Chris Dewhurst2016-10-105-1/+18
| | | | | | | | instruction is not issued, but replaced by SDIVcc instead, which does not exhibit the error. Unit test included. Differential Review: https://reviews.llvm.org/D24660 llvm-svn: 283727
* Fix WebAssembly build after r283702.Daniel Jasper2016-10-101-2/+8
| | | | llvm-svn: 283723
* [AVX-512] Add missing pattern sext or zext from bytes to quad words with a ↵Craig Topper2016-10-101-0/+2
| | | | | | 128-bit load as input. llvm-svn: 283720
* [x86][inline-asm][llvm] accept 'v' constraintMichael Zuckerman2016-10-101-0/+15
| | | | | | | | | | | | | | Commit in the name of:Coby Tayree 1.'v' constraint for (x86) non-avx arch imitates the already implemented 'x' constraint, i.e. allows XMM{0-15} & YMM{0-15} depending on the apparent arch & mode (32/64). 2.for the avx512 arch it allows [X,Y,Z]MM{0-31} (mode dependent) This patch applies the needed changes to clang clang patch: https://reviews.llvm.org/D25004 Differential Revision: D25005 llvm-svn: 283717
* [AVR] Enable generation of the TableGen assembly writer tablesDylan McKay2016-10-101-2/+3
| | | | | | | This also changes the order of the statements in CMakeLists.txt to be alphabetical. llvm-svn: 283711
* [AVX-512] Port 128 and 256-bit memory->register sign/zero extend patterns ↵Craig Topper2016-10-091-0/+142
| | | | | | from SSE file. Also add a minimal set for 512-bit. llvm-svn: 283704
* [X86] Remove redundant patterns. The same pattern appears a few lines up.Craig Topper2016-10-091-6/+0
| | | | llvm-svn: 283703
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-09100-331/+470
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* DAG: Setting Masked-Expand-Load as a variant of Masked-Load nodeElena Demikhovsky2016-10-094-30/+52
| | | | | | | | | | Masked-expand-load node represents load operation that loads a variable amount of elements from memory according to amount of "true" bits in the mask and expands the loaded elements according to their position in the mask vector. Right now, the node is used in intrinsics for VEXPAND* instructions. The work is done towards implementation of masked.expandload and masked.compressstore intrinsics. Differential Revision: https://reviews.llvm.org/D25322 llvm-svn: 283694
* [AVX-512] Fix execution domain for EVEX encoded VINSERTPS.Craig Topper2016-10-091-0/+2
| | | | llvm-svn: 283692
* MC: Remove unused entities.Peter Collingbourne2016-10-0912-22/+14
| | | | llvm-svn: 283691
* Target: Remove unused entities.Peter Collingbourne2016-10-099-51/+4
| | | | llvm-svn: 283690
* [AVX-512] Add subvector insert and extract to load/store folding tables.Craig Topper2016-10-091-0/+25
| | | | llvm-svn: 283689
* [AVX-512] Add the vector down convert instructions to the store folding tables.Craig Topper2016-10-091-0/+24
| | | | llvm-svn: 283687
* Turn cl::values() (for enum) from a vararg function to using C++ variadic ↵Mehdi Amini2016-10-086-12/+6
| | | | | | | | | | | | | | | template The core of the change is supposed to be NFC, however it also fixes what I believe was an undefined behavior when calling: va_start(ValueArgs, Desc); with Desc being a StringRef. Differential Revision: https://reviews.llvm.org/D25342 llvm-svn: 283671
* [AVX-512] Fix a bug in getLargestLegalSuperClass where we inflated to ↵Craig Topper2016-10-081-10/+9
| | | | | | | | VR128X/VR256X even when VLX isn't supported. This seems to have been responsible for the XMM16-31 spills observed in PR29112. With this fixed the test case has been modified to no longer have a spill of XMM16. llvm-svn: 283668
* [Hexagon] Adding change of flow max 1 (cofMax1) TS flag for marking this ↵Colin LeMahieu2016-10-085-4/+16
| | | | | | restriction rather than implying it from TypeJR. llvm-svn: 283665
* [AArch64] Avoid generating indexed vector instructions for ExynosSebastian Pop2016-10-084-0/+376
| | | | | | | | | | | | | | | | | | Avoid generating indexed vector instructions for Exynos. This is needed for fmla/fmls/fmul/fmulx. For example, the instruction fmla v0.4s, v1.4s, v2.s[1] is less efficient than the instructions dup v2.4s, v2.s[1] fmla v0.4s, v1.4s, v2.4s Patch written by Abderrazek Zaafrani. Differential Revision: https://reviews.llvm.org/D21571 llvm-svn: 283663
* [AVR] Add backend dependencies to MCTargetDesc/LLVMBuild.txtDylan McKay2016-10-081-1/+1
| | | | llvm-svn: 283642
* Fix incorrect assertion in AVRFrameLowering.cppDylan McKay2016-10-081-1/+2
| | | | | | This wasn't looking at the right instruction, and would always fail. llvm-svn: 283640
* [AVR] Don't worry about call frame size when initializing frame pointerDylan McKay2016-10-081-3/+2
| | | | | | | | | | | | | We previously only used the frame pointer if the frame pointer was too big. This was to work around a bug (described in this old commit) https://sourceforge.net/p/avr-llvm/code/204/tree//llvm/trunk/AVR/AVRFrameLowering.cpp?diff=50d64d912718465cb887d17a:203 I mistakenly invered the condition assuming it was a typo. I am now removing it because it doesn't seem to be a problem anymore (plus it's a dirty hack). llvm-svn: 283639
* [AVR] Don't shadow container while iterating in range-based loopDylan McKay2016-10-081-2/+4
| | | | | | This works on clang, but fails on GCC 4.6 llvm-svn: 283638
* [AVR] Use references rather than pointers in AVRISelLoweringDylan McKay2016-10-081-2/+2
| | | | llvm-svn: 283636
* Allow a maximum of 64 bits to be returned in registersDylan McKay2016-10-081-0/+8
| | | | | | | | The rest spills to the stack Authored by Jake Goulding llvm-svn: 283635
* [AVR] Expand MULHS for all typesDylan McKay2016-10-081-0/+3
| | | | | | | | | | Once MULHS was expanded, this exposed an issue where the condition register was thought to be 16-bit. This caused an attempt to copy a 16-bit register to an 8-bit register. Authored by Jake Goulding llvm-svn: 283634
* [AVR] Add the 'SoftFail' field to all instruction formatsDylan McKay2016-10-081-0/+2
| | | | | | This will be used in the future for disassembly. llvm-svn: 283630
* [AVR] Set up the instruction printer and the assembly backendDylan McKay2016-10-081-0/+19
| | | | llvm-svn: 283629
* [AVR] Add dependencies to AVR libraries in AVRCodeGenDylan McKay2016-10-081-1/+2
| | | | llvm-svn: 283628
* [AVR] Add missing subdirectories to LLVMBuildDylan McKay2016-10-081-1/+1
| | | | llvm-svn: 283627
* [AVR] Add the assembly printerDylan McKay2016-10-082-0/+183
| | | | | | | | | | | | Summary: This adds the AVRAsmPrinter class. Reviewers: arsenm, kparzysz Subscribers: llvm-commits, wdng, beanz, japaric, mgorny Differential Revision: https://reviews.llvm.org/D25271 llvm-svn: 283623
* AMDGPU/SI: Handle div_fmas hazard in GCNHazardRecognizerTom Stellard2016-10-072-0/+23
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25250 llvm-svn: 283622
* AMDGPU/SI: Add support for 8-byte relocationsTom Stellard2016-10-071-0/+2
| | | | | | | | | | Reviewers: arsenm, kzhuravl Subscribers: wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25375 llvm-svn: 283593
* [Hexagon][NFC] Using documented instruction type name V4LDST instead of MEMOP.Colin LeMahieu2016-10-073-4/+4
| | | | llvm-svn: 283582
* AMDGPU/SI: Emit fixups for long branchesTom Stellard2016-10-071-0/+18
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25366 llvm-svn: 283570
* [AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3.Artem Tamazov2016-10-071-0/+10
| | | | | | | | | Partially fixes Bug 28232. Lit tests added. Differential Revision: https://reviews.llvm.org/D25367 llvm-svn: 283567
* [AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx ↵Sam Kolton2016-10-078-54/+139
| | | | | | | | | | | | to AMDGPUBaseInfo.h Reviewers: artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D25084 llvm-svn: 283560
* [AMDGPU] AMDGPUCodeGenPrepare: remove extra ';'Konstantin Zhuravlyov2016-10-071-1/+1
| | | | llvm-svn: 283558
* [AMDGPU] Promote uniform (i1, i16] operations to i32Konstantin Zhuravlyov2016-10-071-97/+101
| | | | | | Differential Revision: https://reviews.llvm.org/D25302 llvm-svn: 283555
* [ARM]: add missing switch case for cortex-r52Javed Absar2016-10-071-0/+1
| | | | | | | Adds a missing switch case for handling cortex-r52 in init-subtarget-features. llvm-svn: 283551
* [ARM] Reapply: Use __rt_div functions for divrem on WindowsMartin Storsjo2016-10-071-21/+45
| | | | | | | | | | | | | | | | | | | | | | | | Reapplying r283383 after revert in r283442. The additional fix is a getting rid of a stray space in a function name, in the refactoring part of the commit. This avoids falling back to calling out to the GCC rem functions (__moddi3, __umoddi3) when targeting Windows. The __rt_div functions have flipped the two arguments compared to the __aeabi_divmod functions. To match MSVC, we emit a check for division by zero before actually calling the library function (even if the library function itself also might do the same check). Not all calls to __rt_div functions for division are currently merged with calls to the same function with the same parameters for the remainder. This is more wasteful than a div + mls as before, but avoids calls to __moddi3. Differential Revision: https://reviews.llvm.org/D25332 llvm-svn: 283550
* [ARM]: Add Cortex-R52 target to LLVMJaved Absar2016-10-073-4/+24
| | | | | | | This patch adds Cortex-R52, the new ARM real-time processor, to LLVM. Cortex-R52 implements the ARMv8-R architecture. llvm-svn: 283542
* [X86][SSE] Update register class during MOVSD/MOVSS - BLENDPD/BLENDPS ↵Simon Pilgrim2016-10-071-0/+11
| | | | | | | | | | | | | | commutation MOVSD/MOVSS take a 128-bit register and a FR32/FR64 register input, the commutation code wasn't taking this into account leading to verification errors. This patch inserts a vreg copy mi to ensure that the registers are correct. Fix for PR30607 Differential Revision: https://reviews.llvm.org/D25280 llvm-svn: 283539
* [ARM] Don't convert switches to lookup tables of pointers with ROPI/RWPIOliver Stannard2016-10-071-0/+10
| | | | | | | | | | | | With the ROPI and RWPI relocation models we can't always have pointers to global data or functions in constant data, so don't try to convert switches into lookup tables if any value in the lookup table would require a relocation. We can still safely emit lookup tables of other values, such as simple constants. Differential Revision: https://reviews.llvm.org/D24462 llvm-svn: 283530
* Use StringRef in ARMELFStreamer (NFC)Mehdi Amini2016-10-071-2/+2
| | | | llvm-svn: 283529
* AMDGPU: Fix use-after-free in SIOptimizeExecMaskingNicolai Haehnle2016-10-071-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: There was a bug with sequences like s_mov_b64 s[0:1], exec s_and_b64 s[2:3]<def>, s[0:1], s[2:3]<kill> ... s_mov_b64_term exec, s[2:3] because s[2:3] was defined and used in the same instruction, ending up with SaveExecInst inside OtherUseInsts. Note that the test case also exposes an unrelated bug. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98028 Reviewers: tstellarAMD, arsenm Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25306 llvm-svn: 283528
* Use StringReg in TargetParser APIs (NFC)Mehdi Amini2016-10-072-2/+2
| | | | llvm-svn: 283527
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