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* Update call to the new syntax.Bill Wendling2012-11-231-1/+1
| | | | llvm-svn: 168512
* Add more functions to the target library information.Meador Inge2012-11-221-0/+47
| | | | | | | | I discovered a few more missing functions while migrating optimizations from the simplify-libcalls pass to the instcombine (I already added some in r167659). llvm-svn: 168501
* Mips direct object xgot supportJack Carter2012-11-214-1/+45
| | | | | | | | | | | | | | This patch provides support for the MIPS relocations: *) R_MIPS_GOT_HI16 *) R_MIPS_GOT_LO16 *) R_MIPS_CALL_HI16 *) R_MIPS_CALL_LO16 These are used for large GOT instruction sequences. Contributer: Jack Carter llvm-svn: 168471
* [mips] Generate big GOT code.Akira Hatanaka2012-11-215-3/+25
| | | | llvm-svn: 168460
* [mips] Simplify lowering functions in MipsISelLowering.cpp by using the helperAkira Hatanaka2012-11-211-148/+32
| | | | | | functions added in r168456. llvm-svn: 168458
* [mips] Add helper functions that create nodes for computing address.Akira Hatanaka2012-11-211-0/+65
| | | | llvm-svn: 168456
* [mips] Add command line option "-mxgot".Akira Hatanaka2012-11-211-0/+4
| | | | llvm-svn: 168455
* [mips] When a node which loads from a GOT is created, pass a MachinePointerInfoAkira Hatanaka2012-11-211-4/+6
| | | | | | referring to a GOT entry. llvm-svn: 168453
* Add new predicates for the immediate operands.Jyotsna Verma2012-11-211-4/+121
| | | | llvm-svn: 168451
* [mips] Add target operand flag enums for big GOT relocations.Akira Hatanaka2012-11-211-1/+7
| | | | llvm-svn: 168450
* Use one common 'let' expression to set PrintMethod for all immediate operands.Jyotsna Verma2012-11-211-209/+53
| | | | llvm-svn: 168449
* Add support for varargs functions for msp430.Anton Korobeynikov2012-11-213-2/+36
| | | | | | Patch by Job Noorman! llvm-svn: 168440
* Add support for byval args. Patch by Job Noorman!Anton Korobeynikov2012-11-212-17/+46
| | | | llvm-svn: 168439
* Finish the renaming.Rafael Espindola2012-11-212-2/+2
| | | | llvm-svn: 168437
* Renamed HexagonImmediates.td -> HexagonOperands.td.Jyotsna Verma2012-11-212-1/+1
| | | | llvm-svn: 168434
* Fix execution domain for packed FMA4 instructions.Craig Topper2012-11-212-28/+30
| | | | llvm-svn: 168417
* Mark ISD::FMA as Legal instead of custom for x86 with FMA3/FMA4. Needed so ↵Craig Topper2012-11-211-6/+6
| | | | | | that llvm.muladd can be converted to ISD::FMA for fp_contract. llvm-svn: 168413
* Make calcLiveInMask method static.Jakub Staszak2012-11-211-1/+1
| | | | llvm-svn: 168409
* Make isScratchReg and isFPCopy methods static.Jakub Staszak2012-11-211-2/+2
| | | | llvm-svn: 168407
* Add obvious constantness.Jakub Staszak2012-11-201-3/+3
| | | | llvm-svn: 168396
* Removing some unused instruction definitions from the Hexagon backend.Jyotsna Verma2012-11-202-92/+0
| | | | llvm-svn: 168388
* Intel OCL built-ins calling conventions now support MacOS 32-bit.Elena Demikhovsky2012-11-201-23/+24
| | | | llvm-svn: 168359
* Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete ↵Eli Friedman2012-11-171-0/+1
| | | | | | Couperus. llvm-svn: 168240
* Initial implementation of MipsTargetLowering::isLegalAddressingMode.Akira Hatanaka2012-11-172-0/+22
| | | | llvm-svn: 168230
* Rename methods like PairSRegs() to createSRegpairNode() to meet our codingWeiming Zhao2012-11-171-40/+34
| | | | | | style requirement. llvm-svn: 168229
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-166-62/+185
| | | | | | | | | This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
* Make sure FABS on v2f32 and v4f32 is legal on ARM NEONAnton Korobeynikov2012-11-162-7/+9
| | | | | | This fixes PR14359 llvm-svn: 168200
* Fix handling of aliases to functions.Richard Osborne2012-11-161-13/+9
| | | | | | An alias to a function should use pc relative addressing. llvm-svn: 168199
* [NVPTX] Order global variables in def-use order before emiting them in the ↵Justin Holewinski2012-11-161-3/+67
| | | | | | final assembly llvm-svn: 168198
* Using const cast to alleviate a warning.Joe Abbey2012-11-161-1/+2
| | | | | | A PR is being filed to address some code issues here. llvm-svn: 168185
* Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris.Duncan Sands2012-11-163-5/+63
| | | | llvm-svn: 168166
* Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of ↵Craig Topper2012-11-162-0/+68
| | | | | | vector types. llvm-svn: 168141
* [mips] Fix delay slot filler so that instructions with register operand $1 areAkira Hatanaka2012-11-161-17/+34
| | | | | | allowed in branch delay slot. llvm-svn: 168131
* Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missingEli Friedman2012-11-151-0/+2
| | | | | | | | case to vector legalization so this actually works. Patch by Pete Couperus. Fixes PR12540. llvm-svn: 168107
* [mips] Add predicate HasFPIdx for floating-point indexed load instructionAkira Hatanaka2012-11-156-11/+16
| | | | | | support and use it in place of HasMips32r2Or64. llvm-svn: 168089
* PowerPC: Lowering floor intrinsic for AltivecAdhemerval Zanella2012-11-152-0/+14
| | | | | | | | This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and llvm.nearbyint to Altivec instruction when using 4 single-precision float vectors. llvm-svn: 168086
* Add assertions in MipsLongBranch which check the size of basic blocks.Akira Hatanaka2012-11-151-1/+7
| | | | llvm-svn: 168078
* Return 0 instead of false.Jakub Staszak2012-11-151-3/+3
| | | | llvm-svn: 168076
* Simplify code.Jakub Staszak2012-11-151-1/+1
| | | | llvm-svn: 168064
* Use empty parens for empty function parameter list instead of '(void)'.Dmitri Gribenko2012-11-153-3/+3
| | | | llvm-svn: 168049
* Revert changing FNEG of v4f32 to Expand. It's legal.Craig Topper2012-11-151-1/+0
| | | | llvm-svn: 168030
* Make FNEG and FABS of v4f32 Expand.Craig Topper2012-11-151-0/+2
| | | | llvm-svn: 168029
* Make a bunch of floating point operations on vectors Expand so that ↵Craig Topper2012-11-151-6/+10
| | | | | | instruction selection won't fail. llvm-svn: 168028
* Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.Craig Topper2012-11-153-1/+13
| | | | llvm-svn: 168025
* Remove unneeded #includes.Jakub Staszak2012-11-141-3/+0
| | | | llvm-svn: 168006
* NVPTXISelLowering.cpp: Fix warnings. [-Wunused-variable]NAKAMURA Takumi2012-11-141-6/+4
| | | | llvm-svn: 168001
* Remove the CellSPU port.Eric Christopher2012-11-1452-14677/+1
| | | | | | Approved by Chris Lattner. llvm-svn: 167984
* Fix invalid asserts, use llvm_unreachable instead.Jakub Staszak2012-11-141-3/+3
| | | | llvm-svn: 167976
* Added multiclass for post-increment load instructions.Jyotsna Verma2012-11-144-233/+187
| | | | llvm-svn: 167974
* X86: Enable SSE memory intrinsics even when stack alignment is less than 16 ↵Benjamin Kramer2012-11-141-7/+2
| | | | | | | | | | | | | | | | | | bytes. The stack realignment code was fixed to work when there is stack realignment and a dynamic alloca is present so this shouldn't cause correctness issues anymore. Note that this also enables generation of AVX instructions for memset under the assumptions: - Unaligned loads/stores are always fast on CPUs supporting AVX - AVX is not slower than SSE We may need some tweaked heuristics if one of those assumptions turns out not to be true. Effectively reverts r58317. Part of PR2962. llvm-svn: 167967
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