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* Have ARM ELF use correct reloc for "b" instr.Jan Wen Voung2012-06-191-5/+3
| | | | | | | The condition code didn't actually matter for arm "b" instructions, unlike "bl". It should just use the R_ARM_JUMP24 reloc. llvm-svn: 158722
* Mark most PPC register classes to avoid write-after-write.Hal Finkel2012-06-192-0/+16
| | | | | | | | | | | | | | | | | | | | | | | For processors with the G5-like instruction-grouping scheme, this helps avoid early group termination due to a write-after-write dependency within the group. It should also help on pipelined embedded cores. On POWER7, over the test suite, this gives an average 0.5% speedup. The largest speedups are: SingleSource/Benchmarks/Stanford/Quicksort - 33% MultiSource/Applications/d/make_dparser - 21% MultiSource/Benchmarks/FreeBench/analyzer/analyzer - 12% MultiSource/Benchmarks/MiBench/telecomm-FFT/telecomm-fft - 12% Largest slowdowns: SingleSource/Benchmarks/Stanford/Bubblesort - 23% MultiSource/Benchmarks/Prolangs-C++/city/city - 21% MultiSource/Benchmarks/BitBench/uuencode/uuencode - 16% MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode - 13% llvm-svn: 158719
* Make MipsLongBranch::runOnMachineFunction return true.Akira Hatanaka2012-06-191-4/+4
| | | | llvm-svn: 158702
* Use MachineBasicBlock::instr_iterator instead of MachineBasicBlock::iterator inAkira Hatanaka2012-06-191-2/+2
| | | | | | MipsCodeEmitter.cpp. llvm-svn: 158701
* Add support for generating reg+reg preinc stores on PPC.Hal Finkel2012-06-196-25/+114
| | | | | | PPC will now generate STWUX and friends. llvm-svn: 158698
* Move the support for using .init_array from ARM to the genericRafael Espindola2012-06-195-45/+19
| | | | | | | | | | TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM, on X86 it is not easy to find out if .init_array should be used or not, so the decision is made via TargetOptions and defaults to off. Add a command line option to llc that enables it. llvm-svn: 158692
* ARM: use NOEN loads and stores if possible when handling struct byval.Manman Ren2012-06-181-8/+42
| | | | | | | | This change is to be enabled in clang. rdar://9877866 llvm-svn: 158684
* Allow up to 64 functional units per processor itinerary.Hal Finkel2012-06-182-2/+2
| | | | | | | This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. llvm-svn: 158679
* ARM: Define generic HINT instruction.Jim Grosbach2012-06-184-50/+46
| | | | | | | | | | | The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 llvm-svn: 158674
* This change handles a another case for generating the bic instruction Joel Jones2012-06-181-0/+31
| | | | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. The 8 bit case doesn't need to be handled, as the 8 bit constants are encoded directly, thereby not needing a separate load instruction to form the constant into a register. <rdar://problem/11481151> llvm-svn: 158659
* Temporarily revert r158087.Chandler Carruth2012-06-183-93/+14
| | | | | | | | | | | | | This patch causes problems when both dynamic stack realignment and dynamic allocas combine in the same function. With this patch, we no longer build the epilog correctly, and silently restore registers from the wrong position in the stack. Thanks to Matt for tracking this down, and getting at least an initial test case to Chad. I'm going to try to check a variation of that test case in so we can easily track the fixes required. llvm-svn: 158654
* Cleanup trip-count finding for PPC CTR loops (and some bug fixes).Hal Finkel2012-06-161-86/+127
| | | | | | | | | | | | | | This cleans up the method used to find trip counts in order to form CTR loops on PPC. This refactoring allows the pass to find loops which have a constant trip count but also happen to end with a comparison to zero. This also adds explicit FIXMEs to mark two different classes of loops that are currently ignored. In addition, we now search through all potential induction operations instead of just the first. Also, we check the predicate code on the conditional branch and abort the transformation if the code is not EQ or NE, and we then make sure that the branch to be transformed matches the condition register defined by the comparison (multiple possible comparisons will be considered). llvm-svn: 158607
* *no need to pollute Intel syntax with bonus mnemonics; operand size is ↵Kay Tiong Khoo2012-06-161-6/+6
| | | | | | explicitly specified llvm-svn: 158603
* Mips/AsmParser/CMakeLists.txt: Fix dependency.NAKAMURA Takumi2012-06-161-2/+1
| | | | llvm-svn: 158602
* Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,Kevin Enderby2012-06-152-21/+31
| | | | | | iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits. llvm-svn: 158560
* ARM: optimization for sub+abs.Manman Ren2012-06-151-11/+6
| | | | | | | | | | | | | | This patch will optimize abs(x-y) FROM sub, movs, rsbmi TO subs, rsbmi For abs, we will use cmp instead of movs. This is necessary because we already have an existing peephole pass which optimizes away cmp following sub. rdar: 11633193 llvm-svn: 158551
* *fixed to separate mnemonic from operands with tabKay Tiong Khoo2012-06-151-4/+4
| | | | llvm-svn: 158543
* Preserve <undef> flags in ARMExpandPseudo.Jakob Stoklund Olesen2012-06-151-5/+6
| | | | | | This probably mostly shows up in bugpoint-generated code. llvm-svn: 158527
* Move AVX version of convert instructions that write to GPRs to the Op1 table.Craig Topper2012-06-151-9/+13
| | | | llvm-svn: 158497
* Move X86::VCVTTSD2SIrr from the 2 operand to 1 operand MemRegOp table.Pete Cooper2012-06-141-1/+1
| | | | | | | Can someone with more knowledge of this please look at other entries to see if others need moved. llvm-svn: 158474
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-1418-91/+91
| | | | llvm-svn: 158471
* 1. introduce MipsPat in place of Pat in order to exclude those fromAkira Hatanaka2012-06-144-204/+229
| | | | | | | | | being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
* MipsLongBranch.cpp: Tweak llvm::next() to appease msvc.NAKAMURA Takumi2012-06-141-5/+7
| | | | llvm-svn: 158446
* Replace assertion failure for badly formatted CPS instrution with error message.Richard Barton2012-06-141-1/+2
| | | | llvm-svn: 158445
* Cleanup whitespace.Jush Lu2012-06-141-13/+12
| | | | llvm-svn: 158443
* Fix Mips/CMakeLists.txt.Akira Hatanaka2012-06-141-0/+1
| | | | llvm-svn: 158437
* Add file MipsLongBranch.cpp.Akira Hatanaka2012-06-141-0/+416
| | | | llvm-svn: 158436
* Remove code in MipsAsmPrinter and MipsMCInstLower.Akira Hatanaka2012-06-143-30/+2
| | | | llvm-svn: 158434
* Add long branch expansion pass for MIPS.Akira Hatanaka2012-06-142-1/+8
| | | | llvm-svn: 158433
* Add AT to the list of registers clobbered by branches so that it is availableAkira Hatanaka2012-06-141-0/+4
| | | | | | as a scratch register when they are expanded to long branches. llvm-svn: 158432
* In MipsRegisterInfo::eliminateFrameIndex, call Mips::loadImmediateAkira Hatanaka2012-06-141-25/+7
| | | | | | to load an immediate that does not fit into 16-bit. llvm-svn: 158431
* In MipsFrameLowering::emitPrologue and emitEpilogue, call Mips::loadImmediateAkira Hatanaka2012-06-141-39/+16
| | | | | | | | to load an immediate that does not fit into 16-bit. Also, take into consideration the global base register slot on the stack when computing the stack size. llvm-svn: 158430
* Define function MipsInstrInfo::GetInstSizeInBytes, which will be called toAkira Hatanaka2012-06-142-6/+76
| | | | | | | compute the size of basic blocks in a function. Also, define a function which emits a series of instructions to load an immediate. llvm-svn: 158429
* In MipsISelDAGToDAG.cpp, store the global base register to a stack frame object.Akira Hatanaka2012-06-141-3/+10
| | | | | | | Long-branches need access to the global base register to get the destination address. llvm-svn: 158428
* Add methods to MipsFunctionInfo for initializing and accessing the stack frameAkira Hatanaka2012-06-141-1/+23
| | | | | | | | | object for the global base register. This is the first of a series of patches which implements long branch expansion for MIPS. llvm-svn: 158427
* Bundle jump/branch instructions with the instructions in the delay slot inAkira Hatanaka2012-06-132-19/+30
| | | | | | | | | delay slot filler pass of MIPS, per suggestion of Jakob Stoklund Olesen. This change, along with the fix in r158154, enables machine verification to be run after delay slot filling. llvm-svn: 158426
* Implement a DAGCombine in MipsISelLowering.cpp which transforms the followingAkira Hatanaka2012-06-132-4/+34
| | | | | | | | | | pattern: (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) "tjt" is a TargetJumpTable node. llvm-svn: 158419
* Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.Akira Hatanaka2012-06-132-0/+17
| | | | llvm-svn: 158414
* Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.Akira Hatanaka2012-06-131-11/+6
| | | | llvm-svn: 158413
* Implement fastcc calling convention for MIPS.Akira Hatanaka2012-06-132-3/+59
| | | | llvm-svn: 158410
* Fix pattern for MKMSK instruction.Richard Osborne2012-06-131-1/+1
| | | | llvm-svn: 158409
* *typo: Cyles changed to CyclesKay Tiong Khoo2012-06-132-2/+2
| | | | llvm-svn: 158404
* Fix intrinsics for XOP frczss/sd instructions. These instructions only take ↵Craig Topper2012-06-131-12/+6
| | | | | | one source register and zero the upper bits of the destination rather than preserving them. llvm-svn: 158396
* Add another missing 64-bit itinerary definition for the PPC A2 core.Hal Finkel2012-06-131-0/+11
| | | | llvm-svn: 158393
* Clean up trailing blanks in Mips16InstrFormats.tdAkira Hatanaka2012-06-131-46/+46
| | | | | | Patch by Reed Kotler. llvm-svn: 158382
* disable use of directive .set nomicromipsAkira Hatanaka2012-06-131-1/+2
| | | | | | | | until this directive is pushed in gas to open source fsf Patch by Reed Kotler. llvm-svn: 158381
* 1. fix places where immed is used in place of imm to be consistent withAkira Hatanaka2012-06-131-38/+38
| | | | | | | | | non mips16 2. fix some comments to change OPcode->EXTEND for extended instructions Patch by Reed Kotler. llvm-svn: 158378
* Add some missing 64-bit itinerary definitions for the PPC A2 core.Hal Finkel2012-06-121-0/+22
| | | | llvm-svn: 158373
* [arm-fast-isel] Add support for -arm-long-calls.Chad Rosier2012-06-121-41/+57
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 158368
* Split out the PPC instruction class IntSimple from IntGeneral.Hal Finkel2012-06-129-65/+90
| | | | | | | On the POWER7, adds and logical operations can also be handled in the load/store pipelines. We'll call these IntSimple. llvm-svn: 158366
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