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* Also favors NOT64r.Evan Cheng2009-01-211-1/+1
| | | | llvm-svn: 62710
* fix warning in release-asserts mode and spelling of assert.Chris Lattner2009-01-211-3/+2
| | | | llvm-svn: 62699
* Fix a recent regression. ClrOpcode is not set for i8; for i8, ifDan Gohman2009-01-211-2/+3
| | | | | | | we want to clear %ah to zero before a division, just use a zero-extending mov to %al. This fixes PR3366. llvm-svn: 62691
* Fixed build warnings. Restoring changes done in 62600, they were lost in 62655.Sanjiv Gupta2009-01-212-4/+5
| | | | llvm-svn: 62681
* Cleanup whitespace and comments, and tweak someDuncan Sands2009-01-212-9/+11
| | | | | | | prototypes, in operand type legalization. No functionality change. llvm-svn: 62680
* Implement LowerOperationWrapper for legalizer. Sanjiv Gupta2009-01-215-138/+174
| | | | | | Also a few signed comparison fixes. llvm-svn: 62665
* CellSPU:Scott Michel2009-01-218-130/+313
| | | | | | | | | | | | | - Ensure that (operation) legalization emits proper FDIV libcall when needed. - Fix various bugs encountered during llvm-spu-gcc build, along with various cleanups. - Start supporting double precision comparisons for remaining libgcc2 build. Discovered interesting DAGCombiner feature, which is currently solved via custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner insists on inserting one anyway.) - Update README. llvm-svn: 62664
* Favors generating "not" over "xor -1". For example.Evan Cheng2009-01-211-0/+3
| | | | | | | | | | | | | | | | | unsigned test(unsigned a) { return ~a; } llvm used to generate: movl $4294967295, %eax xorl 4(%esp), %eax Now it generates: movl 4(%esp), %eax notl %eax It's 3 bytes shorter. llvm-svn: 62661
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-2022-66/+90
| | | | | | sub-register indices as well. llvm-svn: 62600
* Add a README entry noticed while investigating PR3216.Dan Gohman2009-01-201-0/+22
| | | | llvm-svn: 62558
* DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX ↵Evan Cheng2009-01-191-1/+1
| | | | | | instead of sign extending the low part (in AX/EAX/RAX) into it. llvm-svn: 62519
* Fix 80 col violations.Evan Cheng2009-01-191-2/+2
| | | | llvm-svn: 62518
* Handle ISD::DECLARE with PIC relocation model.Evan Cheng2009-01-191-4/+15
| | | | llvm-svn: 62516
* Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector) has two ↵Evan Cheng2009-01-191-2/+2
| | | | | | | | | | | | | | | | | | | uses so we should make it the second source operand of ISD::OR so 2-address pass won't have to be smart about commuting. %reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8) [ConstantPool + 0] %reg1025<def> = MOVSD2PDrr %reg1024 %reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack-1 + 0] %reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill> %reg1028<def> = MOVPD2SDrr %reg1027<kill> %reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill> %reg1030<def> = CVTSD2SSrr %reg1029<kill> MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4) [FixedStack0 + 0] %reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack0 + 0] RET %reg1031<kill>, %ST0<imp-use,kill> The reason 2-addr pass isn't smart enough to commute the ORPSrr is because it can't look pass the MOVSD2PDrr instruction. llvm-svn: 62505
* Now not UINT_TO_FP is legal (it's marked custom), dag combiner won'tEvan Cheng2009-01-191-1/+8
| | | | | | optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself. llvm-svn: 62504
* Extend thiBill Wendling2009-01-171-11/+12
| | | | llvm-svn: 62415
* Fix MatchAddress bug that's preventing negative displacement from being ↵Evan Cheng2009-01-171-14/+13
| | | | | | folded in 64-bit mode. llvm-svn: 62413
* Temporarily revert my last change. It is causing a bootstrap failure.Bill Wendling2009-01-171-0/+4
| | | | llvm-svn: 62405
* Implement a special algorithm for converting uint_to_fp for i32 values onBill Wendling2009-01-172-49/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86. This code: void f() { uint32_t x; float y = (float)x; } used to be: movl %eax, -8(%ebp) movl [2^52 double], -4(%ebp) movsd -8(%ebp), %xmm0 subsd [2^52 double], %xmm0 cvtsd2ss %xmm0, %xmm0 Is now: movsd [2^52 double], %xmm0 movsd %xmm0, %xmm1 movd %ecx, %xmm2 orps %xmm2, %xmm1 subsd %xmm0, %xmm1 cvtsd2ss %xmm1, %xmm0 This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That will be fixed in a later coalescer fix. llvm-svn: 62404
* CMake: Add lib/Target/IA64/IA64Subtarget.cppOscar Fuentes2009-01-171-0/+1
| | | | llvm-svn: 62394
* Fix PPC ISD::Declare isel and eliminate the need for ↵Evan Cheng2009-01-162-4/+21
| | | | | | PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's. llvm-svn: 62373
* Give IA64 a TargetSubtarget subclass, so that it canDan Gohman2009-01-163-0/+49
| | | | | | implement getSubtargetImpl. llvm-svn: 62369
* Add support for non-zero __builtin_return_address values on X86.Bill Wendling2009-01-161-8/+17
| | | | llvm-svn: 62338
* ARMCompilationCallback should not save / restore vfp registers if vfp is not ↵Evan Cheng2009-01-161-2/+2
| | | | | | available. llvm-svn: 62299
* Initial hazard recognizer support in post-pass scheduling. This includesDan Gohman2009-01-162-5/+0
| | | | | | | a new toy hazard recognizier heuristic which attempts to direct the scheduler to avoid clumping large groups of loads or stores too densely. llvm-svn: 62291
* Generalize the HazardRecognizer interface so that it can be usedDan Gohman2009-01-156-19/+26
| | | | | | | to support MachineInstr-based scheduling in addition to SDNode-based scheduling. llvm-svn: 62284
* Fix Alpha test and support for private linkage.Rafael Espindola2009-01-151-1/+2
| | | | llvm-svn: 62282
* Expand insert/extract of a <4 x i32> with a variable index.Mon P Wang2009-01-151-2/+10
| | | | llvm-svn: 62281
* Add the private linkage.Rafael Espindola2009-01-1519-51/+68
| | | | llvm-svn: 62279
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-1510-10/+10
| | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. llvm-svn: 62275
* Add load-folding table entries for BT*ri8 instructions.Dan Gohman2009-01-151-0/+3
| | | | llvm-svn: 62267
* Make getWidenVectorType const.Dan Gohman2009-01-152-2/+2
| | | | llvm-svn: 62265
* Const-qualify getPreIndexedAddressParts and friends.Dan Gohman2009-01-154-14/+15
| | | | llvm-svn: 62259
* Don't fold address calculations which use negative offsets intoRichard Osborne2009-01-151-2/+2
| | | | | | the ADDRspii addressing mode. llvm-svn: 62258
* Update the operands used when building LDAWSP instructions to match the .tdRichard Osborne2009-01-152-2/+1
| | | | | | changes in the last commit. llvm-svn: 62257
* - Convert remaining i64 custom lowering into custom instruction emissionScott Michel2009-01-157-185/+333
| | | | | | | | | | | | | sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom DAG node types as needed. - i64 mul is now a legal instruction, but emits an instruction sequence that stretches tblgen and the imagination, as well as violating laws of several small countries and most southern US states (just kidding, but looking at a function with 80+ parameters is really weird and just plain wrong.) - Update tests as needed. llvm-svn: 62254
* Add pseudo instructions to the XCore for (load|store|load address) of aRichard Osborne2009-01-143-77/+66
| | | | | | | | | | | frame index. eliminateFrameIndex will replace these instructions with (LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use. This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame pointer elimination. However since they were marked as implicitly using SP they could not be rematerialised. llvm-svn: 62238
* fix memleaksNuno Lopes2009-01-131-0/+2
| | | | llvm-svn: 62198
* BT appears to be available on all >= i386 chips.Dan Gohman2009-01-131-1/+0
| | | | llvm-svn: 62196
* Don't use a BT instruction if the AND has multiple uses.Dan Gohman2009-01-131-1/+3
| | | | llvm-svn: 62195
* Disable the register+memory forms of the bt instructions for now. ThanksDan Gohman2009-01-132-12/+20
| | | | | | | | to Eli for pointing out that these forms don't ignore the high bits of their index operands, and as such are not immediately suitable for use by isel. llvm-svn: 62194
* Add bt instructions that take immediate operands.Dan Gohman2009-01-132-2/+32
| | | | llvm-svn: 62180
* Fix a few more JIT encoding issues in the BT instructions.Dan Gohman2009-01-131-2/+2
| | | | llvm-svn: 62179
* Checking in conditionals, function call, arrays and libcalls implementation.Sanjiv Gupta2009-01-1312-275/+1149
| | | | llvm-svn: 62174
* make -march=cpp handle the nocapture attribute, make it assert if itChris Lattner2009-01-131-22/+19
| | | | | | sees attributes it doesn't know. llvm-svn: 62155
* Use DebugInfo interface to lower dbg_* intrinsics.Devang Patel2009-01-133-5/+8
| | | | llvm-svn: 62127
* Rename getABITypeSize to getTypePaddedSize, asDuncan Sands2009-01-1223-44/+45
| | | | | | suggested by Chris. llvm-svn: 62099
* 80 col violation.Evan Cheng2009-01-101-1/+2
| | | | llvm-svn: 62024
* Removed trailing whitespace from Makefiles.Misha Brukman2009-01-0918-38/+38
| | | | llvm-svn: 61991
* Add load-folding table entries for MOVDQA.Dan Gohman2009-01-091-0/+6
| | | | llvm-svn: 61972
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