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* [Hexagon] Implement HexagonSubtarget::useAA()Krzysztof Parzyszek2017-11-302-1/+14
| | | | llvm-svn: 319477
* [globalisel][tablegen] Add support for relative AtomicOrderingsDaniel Sanders2017-11-301-18/+16
| | | | | | | No test yet because the relevant rules are blocked on the atomic_load, and atomic_store nodes. llvm-svn: 319475
* [Hexagon] Solo instructions cannot be used with new value jumpsKrzysztof Parzyszek2017-11-301-0/+3
| | | | llvm-svn: 319470
* [X86] Promote i8 CTPOP to i32 instead of i16 when we have the POPCNT ↵Craig Topper2017-11-301-1/+1
| | | | | | | | instruction. The 32-bit version is shorter to encode and the zext we emit for the promotion is likely going to be a 32-bit zero extend anyway. llvm-svn: 319468
* [aarch64][globalisel] Legalize G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_*Daniel Sanders2017-11-301-1/+3
| | | | | | | | | | | G_ATOMICRMW_* is generally legal on AArch64. The exception is G_ATOMICRMW_NAND. G_ATOMIC_CMPXCHG_WITH_SUCCESS needs to be lowered to G_ATOMIC_CMPXCHG with an external comparison. Note that IRTranslator doesn't generate these instructions yet. llvm-svn: 319466
* [GlobalISel][IRTranslator] Fix crash during translation of zero sized ↵Amara Emerson2017-11-301-0/+2
| | | | | | | | | | | | loads/stores/args/returns. This fixes PR35358. rdar://35619533 Differential Revision: https://reviews.llvm.org/D40604 llvm-svn: 319465
* [WebAssembly] Revert r319186 "Support bitcasted function addresses with ↵Dan Gohman2017-11-301-0/+5
| | | | | | | | | | | varargs." The patch broke Emscripten's EM_ASM macros, which utiltize unprototyped functions. See https://bugs.llvm.org/show_bug.cgi?id=35385 for details. llvm-svn: 319452
* [CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih2017-11-303-15/+14
| | | | | | | | | | | | | | output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
* [PowerPC] Recommit r314244 with refactoring and off by defaultNemanja Ivanovic2017-11-301-0/+1236
| | | | | | | | | | | | | | | This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
* [X86][AVX512] Tag fcmp/ptest/ternlog instructions scheduler classesSimon Pilgrim2017-11-301-70/+90
| | | | llvm-svn: 319433
* [ARM GlobalISel] Bail out for byvalDiana Picus2017-11-301-1/+7
| | | | | | | Fallback if we have a byval parameter or argument since we don't support them yet. llvm-svn: 319428
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-3026-218/+218
| | | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
* [X86][AVX512] Tag binop/rounding/sae instructions scheduler classesSimon Pilgrim2017-11-301-124/+143
| | | | llvm-svn: 319424
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classesSimon Pilgrim2017-11-302-64/+100
| | | | llvm-svn: 319418
* [SystemZ] Bugfix in adjustSubwordCmp.Jonas Paulsson2017-11-301-4/+11
| | | | | | | | | | | | | | | | Csmith generated a program where a store after load to the same address did not get chained after the new load created during DAG legalizing, and so performed an illegal overwrite of the expected value. When the new zero-extending load is created, the chain users of the original load must be updated, which was not done previously. A similar case was also found and handled in lowerBITCAST. Review: Ulrich Weigand https://reviews.llvm.org/D40542 llvm-svn: 319409
* [X86] Optimize avx2 vgatherqps for v2f32 with v2i64 index type.Craig Topper2017-11-301-7/+12
| | | | | | Normal type legalization will widen everything. This requires forcing 0s into the mask register. We can instead choose the form that only reads 2 elements without zeroing the mask. llvm-svn: 319406
* [X86] Make sure we don't remove sign extends of masks with AVX2 masked gathers.Craig Topper2017-11-301-3/+4
| | | | | | We don't use k-registers and instead use the MSB so we need to make sure we sign extend the mask to the msb. llvm-svn: 319405
* AMDGPU: Allow negative MUBUF vaddr for gfx9Matt Arsenault2017-11-302-4/+21
| | | | | | | | GFX9 does not enable bounds checking for the resource descriptors used for private access, so it should be OK to use vaddr with a potentially negative value. llvm-svn: 319393
* [X86] Remove some questionable looking code that seems to be looking through ↵Craig Topper2017-11-291-1/+1
| | | | | | | | | | a VZEXT to create a larger VSEXT. If the input the vzext was signed this would do the wrong thing. Not sure how to test this. llvm-svn: 319382
* First step towards more human-friendly PPC assembler output:Joerg Sonnenberger2017-11-293-32/+74
| | | | | | | | | | | | | | - add -ppc-reg-with-percent-prefix option to use %r3 etc as register names - split off logic for Darwinish verbose conditional codes into a helper function - be explicit about Darwin vs AIX vs GNUish assembler flavors Based on the patch from Alexandre Yukio Yamashita Differential Revision: https://reviews.llvm.org/D39016 llvm-svn: 319381
* [WebAssembly] Update test expectations for gcc torture testsSam Clegg2017-11-291-6/+0
| | | | | | | | | I believe these were recently fixed by: https://reviews.llvm.org/rL319186 Differential Revision: https://reviews.llvm.org/D40619 llvm-svn: 319380
* [WebAssembly] Fix fptoui lowering boundsDan Gohman2017-11-292-14/+47
| | | | | | | To fully avoid trapping on wasm, fptoui needs a second check to ensure that the operand isn't below the supported range. llvm-svn: 319354
* [Hexagon] Remove HexagonISD::PACKHLKrzysztof Parzyszek2017-11-293-6/+1
| | | | llvm-svn: 319352
* [Hexagon] Create helpers extractVector and insertVector in loweringKrzysztof Parzyszek2017-11-292-139/+144
| | | | llvm-svn: 319351
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes (REVERSION)Simon Pilgrim2017-11-292-80/+53
| | | | | | Accidental commit of incomplete patch llvm-svn: 319346
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classesSimon Pilgrim2017-11-292-53/+80
| | | | llvm-svn: 319338
* [X86][AVX512] Tag 3OP (shuffles, double-shifts and GFNI) instructions ↵Simon Pilgrim2017-11-291-76/+91
| | | | | | scheduler classes llvm-svn: 319337
* [ARM][DAG] Revert Disable post-legalization store merge for ARMNirav Dave2017-11-291-0/+3
| | | | | | | | Partially reverting enabling of post-legalization store merge (r319036) for just ARM backend as it is causing incorrect code in some Thumb2 cases. llvm-svn: 319331
* [X86][AVX512] Add itinerary argument to all AVX512_maskable_* wrappers. NFCISimon Pilgrim2017-11-291-44/+49
| | | | | | All default to NoItinerary llvm-svn: 319326
* Reverted r319315 because of unused functions (due to PPR not yet beingSander de Smalen2017-11-293-178/+10
| | | | | | used by any instructions). llvm-svn: 319321
* [X86][AVX512] Tag VPERMILV instruction scheduler classSimon Pilgrim2017-11-292-17/+32
| | | | llvm-svn: 319316
* [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen2017-11-293-10/+178
| | | | | | | | | | | | | | Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40360 llvm-svn: 319315
* [ARM GlobalISel] Fix selecting G_BRCONDDiana Picus2017-11-291-1/+1
| | | | | | | | | | | | | When lowering a G_BRCOND, we generate a TSTri of the condition against 1, which sets the flags, and then a Bcc which branches based on the value of the flags. Unfortunately, we were using the wrong condition code to check whether we need to branch (EQ instead of NE), which caused all our branches to do the opposite of what they were intended to do. This patch fixes the issue by using the correct condition code. llvm-svn: 319313
* [X86][AVX512] Setup unary (PABS/VPLZCNT/VPOPCNT/VPCONFLICT/VMOV*DUP) ↵Simon Pilgrim2017-11-292-55/+84
| | | | | | instruction scheduler classes llvm-svn: 319312
* [AMDGPU][MC][GFX9] Corrected mapping of GFX9 v_add/sub/subrev_u32Dmitry Preobrazhensky2017-11-291-9/+14
| | | | | | | | | | | When translating pseudo to MC, v_add/sub/subrev_u32 shall be mapped via a separate table as GFX8 has opcodes with the same names. These instructions shall also be labelled as renamed for pseudoToMCOpcode to handle them correctly. Reviewers: arsenm Differential Revision: https://reviews.llvm.org/D40550 llvm-svn: 319311
* [X86][SSE] Merged sse2_unpack and sse2_unpack PUNPCK instruction templates. ↵Simon Pilgrim2017-11-291-71/+69
| | | | | | NFCI. llvm-svn: 319310
* [X86][SSE] Merged sse2_pack and sse2_pack_y PACKSS/PACKUS instruction ↵Simon Pilgrim2017-11-291-78/+46
| | | | | | templates. NFCI. llvm-svn: 319308
* [ARM] Add support for armv7e-m to the .arch directiveOliver Stannard2017-11-291-0/+1
| | | | | | | | | | | This will allow compilation of assembly files targeting armv7e-m without having to specify the Tag_CPU_arch attribute as a workaround. Differential revision: https://reviews.llvm.org/D40370 Patch by Ian Tessier! llvm-svn: 319303
* [X86] Remove setOperationAction Promote for ISD::SINT_TO_FP ↵Craig Topper2017-11-291-3/+0
| | | | | | | | MVT::v8i16/v16i8/v16i16. A DAG combine ensures these ops are always promoted to vXi32. llvm-svn: 319298
* [PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended.Sean Fertile2017-11-291-3/+31
| | | | | | | | | | | | Separate the handling of AND/AND8 out from PHI/OR/ISEL checking. The reasoning is the others need all their operands to be sign/zero extended for their output to also be sign/zero extended. This is true for AND and sign-extension, but for zero-extension we only need at least one of the input operands to be zero extended for the result to also be zero extended. Differential Revision: https://reviews.llvm.org/D39078 llvm-svn: 319289
* DAG: Add nuw when splitting loads and storesMatt Arsenault2017-11-292-15/+8
| | | | | | | | | | | The object can't straddle the address space wrap around, so I think it's OK to assume any offsets added to the base object pointer can't overflow. Similar logic already appears to be applied in SelectionDAGBuilder when lowering aggregate returns. llvm-svn: 319272
* AMDGPU: Select DS insts without m0 initializationMatt Arsenault2017-11-296-77/+178
| | | | | | | | | GFX9 stopped using m0 for most DS instructions. Select a different instruction without the use. I think this will be less error prone than trying to manually maintain m0 uses as needed. llvm-svn: 319270
* [X86] Promote fp_to_sint v16f32->v16i16/v16i8 to avoid scalarization.Craig Topper2017-11-291-0/+2
| | | | llvm-svn: 319266
* [X86] Mark ISD::FP_TO_UINT v16i8/v16i16 as Promote under AVX512 instead of ↵Craig Topper2017-11-282-7/+2
| | | | | | | | | | legal. Fix infinite loop in op legalization when promotion requires 2 steps. Previously we had an isel pattern to add the truncate. Instead use Promote to add the truncate to the DAG before isel. The Promote legalization code had to be updated to prevent an infinite loop if promotion took multiple steps because it wasn't remembering the previously tried value. llvm-svn: 319259
* AMDGPU: Enable IPRAMatt Arsenault2017-11-281-0/+4
| | | | llvm-svn: 319256
* [X86] Tag CLFLUSHOPT with same scheduling behaviour as CLFLUSHSimon Pilgrim2017-11-281-2/+3
| | | | llvm-svn: 319253
* [X86][SSE] Add SSE_SHUFP OpndItinsSimon Pilgrim2017-11-281-11/+16
| | | | | | | | Update multi-classes to take the scheduling OpndItins instead of hard coding it. Will be reused in the AVX512 equivalents. llvm-svn: 319249
* [X86][SSE] Add SSE_UNPCK/SSE_PUNPCK OpndItinsSimon Pilgrim2017-11-281-49/+61
| | | | | | | | Update multi-classes to take the scheduling OpndItins instead of hard coding it. Will be reused in the AVX512 equivalents. llvm-svn: 319245
* [X86][SSE] Use SSE_PACK OpndItins in PACKSS/PACKUS instruction definitionsSimon Pilgrim2017-11-281-30/+30
| | | | | | | | Update multi-classes to take the scheduling OpndItins instead of hard coding it. SSE_PACK will be reused in the AVX512 equivalents. llvm-svn: 319243
* Fix VS2017 narrowing conversion warning. NFCISimon Pilgrim2017-11-281-1/+1
| | | | llvm-svn: 319240
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