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* Remove 256-bit AVX non-temporal store intrinsics. Similar was previously ↵Craig Topper2012-05-081-7/+0
| | | | | | done for 128-bit. llvm-svn: 156375
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-0718-25/+40
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Fix bug in TRI::getCommonSuperRegClass().Jakob Stoklund Olesen2012-05-071-0/+1
| | | | | | Test cases for this code are coming. It is not used for anything yet. llvm-svn: 156327
* Add TRI::getCommonSuperRegClass().Jakob Stoklund Olesen2012-05-071-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | This function is a generalization of getMatchingSuperRegClass() to the symmetric case where both sides are using a sub-register index. It will find a super-register class and sub-register indexes that make this diagram commute: PreA SuperRC ----------> RCA | | | | PreB | | SubA | | | | V V RCB ----------> SubRC SubB This can be used to coalesce copies like: %vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2 llvm-svn: 156317
* Fix a regression from r147481. This combine should only happen if there is aChad Rosier2012-05-071-10/+12
| | | | | | | single use. rdar://11360370 llvm-svn: 156316
* X86: optimization for -(x != 0)Manman Ren2012-05-072-0/+22
| | | | | | | | | | | | | | | | | This patch will optimize -(x != 0) on X86 FROM cmpl $0x01,%edi sbbl %eax,%eax notl %eax TO negl %edi sbbl %eax %eax In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td: def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; rdar: 10961709 llvm-svn: 156312
* Add support for the 'x' constraint.Eric Christopher2012-05-071-1/+8
| | | | | | Patch by Jack Carter. llvm-svn: 156295
* Add support for the 'l' constraint.Eric Christopher2012-05-071-0/+7
| | | | | | Patch by Jack Carter. llvm-svn: 156294
* Add support for the 'c' constraint.Eric Christopher2012-05-071-1/+13
| | | | | | Patch by Jack Carter. llvm-svn: 156293
* Add support for the 'P' constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156292
* Fix some issues in the f16c instructions.Craig Topper2012-05-071-11/+9
| | | | llvm-svn: 156287
* Add support for the 'O' constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156285
* Add support for the 'N' inline asm constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156284
* Add support for the 'L' inline asm constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156283
* Add support for the inline asm constraint 'K'.Eric Christopher2012-05-071-0/+11
| | | | llvm-svn: 156282
* Add SSE4A MOVNTSS/MOVNTSD instructions.Craig Topper2012-05-071-0/+14
| | | | llvm-svn: 156281
* Support the 'J' constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156280
* Add support for the 'I' inline asm constraint. Also add testsEric Christopher2012-05-072-0/+48
| | | | | | | | from the previous 2 patches. Patch by Jack Carter. llvm-svn: 156279
* Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.Eric Christopher2012-05-071-2/+4
| | | | | | Patch by Jack Carter. llvm-svn: 156278
* When using inline asm constraints representingEric Christopher2012-05-071-1/+1
| | | | | | | | | non-floating point general registers allow 8 and 16-bit elements. Patch by Jack Carter. llvm-svn: 156277
* Use MVT instead of EVT as the argument to all the shuffle decode functions. ↵Craig Topper2012-05-063-35/+33
| | | | | | Simplify some of the decode functions. llvm-svn: 156268
* Add VPERMQ/VPERMPD to the list of target specific shuffles that can be ↵Craig Topper2012-05-061-0/+6
| | | | | | looked through for DAG combine purposes. llvm-svn: 156266
* Add shuffle decode support for VPERMQ/VPERMPD.Craig Topper2012-05-063-0/+22
| | | | llvm-svn: 156265
* Nuke a few dead remnants of the CBE.Jim Grosbach2012-05-052-44/+0
| | | | llvm-svn: 156241
* Add a new target hook "predictableSelectIsExpensive".Benjamin Kramer2012-05-052-0/+6
| | | | | | | | | | | This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) llvm-svn: 156233
* NVPTX: Initialize the UseF32FTZ flag.Benjamin Kramer2012-05-051-0/+2
| | | | llvm-svn: 156232
* Typo.Eric Christopher2012-05-051-1/+1
| | | | llvm-svn: 156226
* Fix warnings in release build.David Blaikie2012-05-042-1/+2
| | | | | | | | | This fixes a couple of Clang warnings in release builds of LLVM: * Missing return in ISelLowering * Unused variable in NVPTXutil.cpp llvm-svn: 156216
* Tweak to the fix in r156212, as with the change in removing the shift theKevin Enderby2012-05-041-1/+1
| | | | | | SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) . llvm-svn: 156213
* Fix a bug in the ARM disassembler for wide branch conditional instructionsKevin Enderby2012-05-041-1/+1
| | | | | | | where the symbolic operand's displacement was incorrectly shifted left by 1. rdar://11387046 llvm-svn: 156212
* Fix a Clang warning in the new NVPTX backend:Chandler Carruth2012-05-041-1/+1
| | | | | | | | | | | | | | In file included from ../lib/Target/NVPTX/VectorElementize.cpp:53: ../lib/Target/NVPTX/NVPTX.h:44:3: warning: default label in switch which covers all enumeration values [-Wcovered-switch-default] default: assert(0 && "Unknown condition code"); ^ 1 warning generated. The prevailing pattern in LLVM is to not use a default label, and instead to use llvm_unreachable to denote that the switch in fact covers all return paths from the function. llvm-svn: 156209
* This patch adds a new NVPTX back-end to LLVM which supports code generation ↵Justin Holewinski2012-05-0460-1/+22984
| | | | | | | | | | | | | | | | | for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB llvm-svn: 156196
* Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits ↵Sebastian Pop2012-05-041-0/+1
| | | | | | 16-bits encoding of CMN instructions. llvm-svn: 156195
* Adds Intel Atom scheduling latencies to X86InstrSystem.td.Preston Gurd2012-05-043-139/+272
| | | | llvm-svn: 156194
* Pacify GCC's -Wreturn-typeMatt Beaumont-Gay2012-05-041-0/+1
| | | | llvm-svn: 156189
* Make ARM and Mips use TargetMachine::getTLSModel()Hans Wennborg2012-05-043-12/+23
| | | | | | | | This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). llvm-svn: 156162
* Fix some loops to match coding standards. No functional change intended.Craig Topper2012-05-041-6/+8
| | | | llvm-svn: 156159
* Fix up some spacing. No functional change.Craig Topper2012-05-041-6/+6
| | | | llvm-svn: 156158
* Simplify broadcast lowering code. No functional change intended.Craig Topper2012-05-041-17/+7
| | | | llvm-svn: 156157
* Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles.Craig Topper2012-05-041-5/+8
| | | | llvm-svn: 156156
* Simplify shuffle narrowing code a bit. No functional change intended.Craig Topper2012-05-041-22/+16
| | | | llvm-svn: 156154
* Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen2012-05-046-121/+30
| | | | | | This information in now computed by TableGen. llvm-svn: 156152
* Initialize SparcInstrInfo before SparcTargetLowering.Jakob Stoklund Olesen2012-05-042-2/+3
| | | | | | | The TargetLowering construction needs to use a valid TargetRegisterInfo instance. llvm-svn: 156146
* Add a SuperRegClassIterator class.Jakob Stoklund Olesen2012-05-041-15/+13
| | | | | | | | This iterator class provides a more abstract interface to the (Idx, Mask) lists of super-registers for a register class. The layout of the tables shouldn't be exposed to clients. llvm-svn: 156144
* Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-0/+30
| | | | | | TargetRegisterClass now gives access to the necessary tables. llvm-svn: 156122
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-033-42/+99
| | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! llvm-svn: 156118
* Support for target dependent Hexagon VLIW packetizer.Sirish Pande2012-05-0314-93/+4967
| | | | | | This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-031-4/+6
| | | | llvm-svn: 156077
* Extensions of Hexagon V4 instructions.Sirish Pande2012-05-039-1339/+4107
| | | | | | This adds new instructions for Hexagon V4 architecture. llvm-svn: 156071
* Use 'unsigned' instead of 'int' in a few places dealing with counts of ↵Craig Topper2012-05-031-3/+3
| | | | | | vector elements. llvm-svn: 156060
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