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* This patch represents Mips utilization of r186388 code that alows asm ↵Vladimir Medic2013-07-164-270/+242
| | | | | | matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. llvm-svn: 186397
* PPCJITInfo.cpp: Tweak r186252 with s/__ppc/__powerpc/ to work on ↵NAKAMURA Takumi2013-07-161-2/+2
| | | | | | | | powerpc-linux Fedora 12. g++ (GCC) 4.4.4 20100630 (Red Hat 4.4.4-10) llvm-svn: 186396
* ARM: implement ldrex, strex and clrex intrinsicsTim Northover2013-07-165-16/+131
| | | | | | | Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
* ARM EABI divmod supportRenato Golin2013-07-163-2/+87
| | | | | | | | | | | | This patch enables calls to __aeabi_idivmod when in EABI mode, by using the remainder value returned on registers (R1), enabled by the ARM triple "none-eabi". Note that Darwin and GNUEABI triples will continue lowering on GNU style, that is, using the stack for the remainder. Still need to add SREM/UREM support fix for 64-bit lowering. llvm-svn: 186390
* Add 'const' qualifiers to static const char* variables.Craig Topper2013-07-161-7/+7
| | | | llvm-svn: 186371
* PPC: Refactoring to support subtarget feature changingHal Finkel2013-07-152-37/+69
| | | | | | | | | This change mirrors the changes that were made to the X86 and ARM targets to support subtarget feature changing. As indicated in r182899, the mechanism is still undergoing revision, and so as with the X86 and ARM targets, there is no test case yet (there is no effective functionality change). llvm-svn: 186357
* Fix register subclass handling in PPCInstrInfo::insertSelectHal Finkel2013-07-151-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | PPCInstrInfo::insertSelect and PPCInstrInfo::canInsertSelect were computing the common subclass of the true and false inputs, and then selecting either the 32-bit or the 64-bit isel variant based on the result of calling PPC::GPRCRegClass.hasSubClassEq(RC) and PPC::G8RCRegClass.hasSubClassEq(RC) (where RC is the common subclass). Unfortunately, this is not quite right: if we have something like this: %vreg8<def> = SELECT_CC_I8 %vreg4<kill>, %vreg7<kill>, %vreg6<kill>, 76; G8RC_and_G8RC_NOX0:%vreg8 CRRC:%vreg4 G8RC_NOX0:%vreg7,%vreg6 then the common subclass of G8RC_and_G8RC_NOX0 and G8RC_NOX0 is G8RC_NOX0, and G8RC_NOX0 is not a subclass of G8RC (because it also contains the ZERO8 pseudo-register). As a result, we also need to check the common subclass against GPRC_NOR0 and G8RC_NOX0 explicitly. This had not been a problem for clients of insertSelect that called canInsertSelect first (because it had a compensating mistake), but insertSelect is also used by the PPC pseudo-instruction expander, and this error was causing a problem in that context. This problem was found by csmith. llvm-svn: 186343
* R600/SI: Add support for 64-bit loadsTom Stellard2013-07-153-1/+29
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=65873 llvm-svn: 186339
* Test commit to see if write access works.Job Noorman2013-07-151-1/+1
| | | | llvm-svn: 186321
* Make some arrays 'static const'Craig Topper2013-07-153-43/+51
| | | | llvm-svn: 186311
* Add const qualifier to some static arrays.Craig Topper2013-07-152-6/+6
| | | | llvm-svn: 186309
* Add 'static' keyword to some const arrays for consistency.Craig Topper2013-07-151-6/+6
| | | | llvm-svn: 186308
* Make some arrays 'static const'Craig Topper2013-07-154-11/+11
| | | | llvm-svn: 186307
* Use llvm::array_lengthof to replace sizeof(array)/sizeof(array[0]).Craig Topper2013-07-154-7/+7
| | | | llvm-svn: 186301
* Use conventional syntax for branches.Anton Korobeynikov2013-07-141-2/+2
| | | | | | Patch by Job! llvm-svn: 186291
* Properly lower jump tables on MSP430. Patch by Job Noorman!Anton Korobeynikov2013-07-141-2/+2
| | | | llvm-svn: 186283
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-1425-79/+79
| | | | | | size. llvm-svn: 186274
* Reduce large list of macros to the primary platform macros. DistingiushJoerg Sonnenberger2013-07-131-20/+18
| | | | | | | between ELF (Linux, FreeBSD, NetBSD) and OSX as platform for the assembler dialect. llvm-svn: 186252
* [mips] Implement MipsTargetMachine::getInstrItineraryData().Akira Hatanaka2013-07-123-2/+9
| | | | llvm-svn: 186227
* Fix ARM paired GPR COPY loweringJF Bastien2013-07-121-0/+3
| | | | | | | | | | | | | ARM paired GPR COPY was being lowered to two MOVr without CC. This patch puts the CC back. My test is a reduction of the case where I encountered the issue, 64-bit atomics use paired GPRs. The issue only occurs with selectionDAG, FastISel doesn't encounter it so I didn't bother calling it. llvm-svn: 186226
* [mips] Add instruction itinerary classes for mult, seb and slt instructions.Akira Hatanaka2013-07-123-13/+16
| | | | llvm-svn: 186222
* Remove extraneous braces.Eric Christopher2013-07-121-6/+3
| | | | llvm-svn: 186212
* R600: Remove unsafe type punning. No intended functionality change.Benjamin Kramer2013-07-121-6/+4
| | | | llvm-svn: 186196
* X86 cost model: Add cost for vectorized gather/scatherArnold Schwaighofer2013-07-121-0/+15
| | | | | | radar://14351991 llvm-svn: 186189
* ARM cost model: Add cost for gather/scatherArnold Schwaighofer2013-07-121-0/+9
| | | | | | | | | | Fixes a 35% degradation compared to unvectorized code in MiBench/automotive-susan and an equally serious regression on a private image processing benchmark. radar://14351991 llvm-svn: 186188
* TargetTransformInfo: address calculation parameter for gather/scatherArnold Schwaighofer2013-07-121-2/+2
| | | | | | | | | | | Address calculation for gather/scather in vectorized code can incur a significant cost making vectorization unbeneficial. Add infrastructure to add cost. Tests and cost model for targets will be in follow-up commits. radar://14351991 llvm-svn: 186187
* R600/SI: Add support for f64 kernel argumentsTom Stellard2013-07-121-1/+1
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186182
* R600/SI: Implement select and compares for SITom Stellard2013-07-121-6/+18
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186181
* R600/SI: Add fsqrt pattern for SITom Stellard2013-07-121-2/+6
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186180
* R600/SI: Add double precision fsub pattern for SITom Stellard2013-07-122-3/+29
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186179
* R600/SI: SI support for 64bit ConstantFPTom Stellard2013-07-122-0/+19
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186178
* R600/SI: Add initial double precision support for SITom Stellard2013-07-123-1/+36
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186177
* X86: Shrink certain forms of movsx.Benjamin Kramer2013-07-121-0/+35
| | | | | | | | | | | | In particular: movsbw %al, %ax --> cbtw movswl %ax, %eax --> cwtl movslq %eax, %rax --> cltq According to Intel's manual those have the same performance characteristics but come with a smaller encoding. llvm-svn: 186174
* X86: fold SSE2/AVX2 logical shift by immediate amount into zero vector when ↵Stephen Lin2013-07-121-0/+38
| | | | | | | | possible Patch by Andrea Di Biagio llvm-svn: 186165
* Add support for Mips break and syscall insructions. The corresponding test ↵Vladimir Medic2013-07-122-0/+49
| | | | | | cases are added. llvm-svn: 186151
* [SystemZ] Optimize sign-extends of vector setccsRichard Sandiford2013-07-121-0/+9
| | | | | | | | | | | | | Normal (sext (setcc ...)) sequences are optimised into (select_cc ..., -1, 0) by DAGCombiner::visitSIGN_EXTEND. However, this is deliberately not done for vectors, and after vector type legalization we have (sext_inreg (setcc ...)) instead. I wondered about trying to extend DAGCombiner to handle this case too, but it seemed to be a loss on some other targets I tried, even those for which SETCC isn't "legal" and SELECT_CC is. llvm-svn: 186149
* [SystemZ] Fix parsing of inline asm registersRichard Sandiford2013-07-124-8/+49
| | | | | | | | | | | | GPR and FPR constraints like "{r2}" and "{f2}" weren't handled correctly because the name-to-regno mapping depends on the value type and (because of that) the internal names in RegStrings are not the same as the AsmName. CC constraints like "{cc}" didn't work either because there was no associated register class. llvm-svn: 186148
* [SystemZ] Improve spilling of LGDR and LDGRRichard Sandiford2013-07-121-1/+23
| | | | | | | If the source of these instructions is spilled we should load the destination. If the destination is spilled we should store the source. llvm-svn: 186147
* Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.Charles Davis2013-07-124-25/+45
| | | | | | | | | | | | | | | Summary: This patch adds explicit calling convention types for the Win64 and System V/x86-64 ABIs. This allows code to override the default, and use the Win64 convention on a target that wants to use SysV (and vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU attributes. Reviewers: CC: llvm-svn: 186144
* PPC: Add some missing V_SET0 patternsHal Finkel2013-07-111-2/+15
| | | | | | | | | | We had patterns to match v4i32 immAllZerosV -> V_SET0, but not patterns for v8i16 (which occurs in the test case) or v16i8. The same was true for V_SETALLONES (so I added the associated patterns for those as well). Another bug found by llvm-stress. llvm-svn: 186108
* PPCDAGToDAGISel::isRunOfOnes should return false on zeroHal Finkel2013-07-111-1/+4
| | | | | | | | | | | | This fixes a bug (found by csmith) at -O0 where we attempt to create a RLWIMI with an out-of-range operand. Most uses of the isRunOfOnes function are guarded by a condition that the value is not zero. This was not true in two places, and in both places a zero input would result in an out-of-rage MB value (= 32). To fix this, isRunOfOnes returns false on a zero input (and I've remove one now-redundant guard). llvm-svn: 186101
* [SystemZ] Use zeroing form of RISBG for shift-and-AND sequencesRichard Sandiford2013-07-111-5/+66
| | | | | | Extend r186072 to handle shifts and ANDs. llvm-svn: 186073
* [SystemZ] Use zeroing form of RISBG for some AND sequencesRichard Sandiford2013-07-111-1/+118
| | | | | | | | | | | | RISBG can handle some ANDs for which no AND IMMEDIATE exists. It also acts as a three-operand AND for some cases where an AND IMMEDIATE could be used instead. It might be worth adding a pass to replace RISBG with AND IMMEDIATE in cases where the register operands end up being the same and where AND IMMEDIATE is smaller. llvm-svn: 186072
* [SystemZ] Allow 8-bit operands to RISBGRichard Sandiford2013-07-111-2/+1
| | | | | | | | | | | | RISBG has three 8-bit operands (I3, I4 and I5). I'd originally restricted all three to 6 bits, since that's the only range we intended to use at the time. However, the top bit of I4 acts as a "zero" flag for RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co. This patch therefore allows them to have the full 8-bit range. I've left the fifth operand as a 6-bit value for now since the upper 2 bits have no defined meaning. llvm-svn: 186070
* Replacing an empty switch with its moral equivalent. No functional changes ↵Aaron Ballman2013-07-102-8/+2
| | | | | | intended. llvm-svn: 186017
* Simplify code.Craig Topper2013-07-101-6/+2
| | | | llvm-svn: 186013
* R600/SI: Initial local memory supportMichel Danzer2013-07-106-3/+34
| | | | | | | Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012
* R600/SI: Add pattern for the AMDGPU.barrier.local intrinsicMichel Danzer2013-07-101-1/+10
| | | | | | | lit test coverage to follow in the next commit. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186011
* R600/SI: Add intrinsic for retrieving the current thread IDMichel Danzer2013-07-102-2/+9
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186010
* R600/SI: Initial support for LDS/GDS instructionsMichel Danzer2013-07-105-0/+68
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186009
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