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* 142288 broke the build:Rafael Espindola2011-10-171-88/+25
| | | | | | | | | | | | Linking CXX executable ../../bin/llvm-as ../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)' clang-3: error: linker command failed with exit code 1 (use -v to see invocation) Revert "Validate target data layout strings." This reverts commit 599d2d4c25d3aee63a21d9c67a88cd43bd971b7e. llvm-svn: 142296
* Now Igor, throw the switch...give my creation life!Bill Wendling2011-10-173-4/+8
| | | | | | | | | | | | | | | | | Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the SjLj dispatch table in IR, where it frequently violates serveral assumptions -- in particular assumptions made by the landingpad instruction about what can branch to a landing pad and what cannot. Performing this in the back-end allows us to violate these assumptions without the IR getting angry at us. It also allows us to perform a small optimization. We can shove the address of the dispatch's basic block into the function context and not have to add code around the setjmp to check for the return value and jump to the dispatch. Neat, huh? <rdar://problem/10116753> llvm-svn: 142294
* ARM NEON "vmov.i8" immediate assembly parsing and encoding.Jim Grosbach2011-10-172-3/+45
| | | | | | | | NEON immediates are "interesting". Start of the work to handle parsing them in an 'as' compatible manner. Getting the matcher to play nicely with these and the floating point immediates from VFP is an extra fun wrinkle. llvm-svn: 142293
* Validate target data layout strings.Lang Hames2011-10-171-25/+88
| | | | | | Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion. llvm-svn: 142288
* Use a SmallVector for intrinsic argument types.Benjamin Kramer2011-10-172-2/+2
| | | | llvm-svn: 142259
* Don't renumber the blocks here. This could cause problems later on if anotherBill Wendling2011-10-171-3/+1
| | | | | | pass renumbers the blocks again. llvm-svn: 142258
* Pseudoinstructions should not be less constrained than the instruction they areCameron Zwarich2011-10-171-6/+6
| | | | | | lowered to. This fixes a lot of verifier failures on the test suite. llvm-svn: 142254
* Tidy up organization.Jim Grosbach2011-10-171-8/+4
| | | | llvm-svn: 142248
* Add a call to EmitSjLjDispatchBlock.Bill Wendling2011-10-171-0/+8
| | | | | | | Once the intrinsics are marked as having a custom inserter, it will call this method to emit the dispatch table into the machine function. llvm-svn: 142245
* Fix improperly formed assert() call.Jim Grosbach2011-10-171-1/+1
| | | | llvm-svn: 142239
* Add definitions of conditional moves with 64-bit operands. Comment out code forAkira Hatanaka2011-10-173-75/+130
| | | | | | | expanding conditional moves, which is not needed since architectures that lack support for conditional moves have been removed. llvm-svn: 142226
* Revert change to function alignment b/c existing logic was fineHal Finkel2011-10-171-10/+3
| | | | llvm-svn: 142224
* Removed set, but unused variables.Chad Rosier2011-10-172-12/+0
| | | | | | Patch by Joe Abbey <jabbey@arxan.com>. llvm-svn: 142223
* Move class and instruction definitions for conditional moves to a seperate file.Akira Hatanaka2011-10-174-106/+112
| | | | llvm-svn: 142220
* Revert change made in r142205.Akira Hatanaka2011-10-171-2/+2
| | | | llvm-svn: 142217
* Redefine count-leading 0s and 1s instructions.Akira Hatanaka2011-10-172-20/+17
| | | | llvm-svn: 142216
* Redefine mfhi/lo and mthi/lo instructions.Akira Hatanaka2011-10-172-35/+16
| | | | llvm-svn: 142214
* Redefine multiply and divide instructions.Akira Hatanaka2011-10-172-25/+26
| | | | llvm-svn: 142211
* Add definition of a base class for logical shift/rotate instructions with twoAkira Hatanaka2011-10-172-20/+12
| | | | | | source registers and redefine 32-bit and 64-bit instructions. llvm-svn: 142210
* Remove >80-col line and unicodeHal Finkel2011-10-171-2/+2
| | | | llvm-svn: 142209
* Add definition of a base class for logical shift/rotate immediate instructionsAkira Hatanaka2011-10-172-27/+33
| | | | | | and have 32-bit and 64-bit instructions derive from it. llvm-svn: 142207
* Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.Akira Hatanaka2011-10-173-9/+11
| | | | llvm-svn: 142205
* Fix CMake build.Michael J. Spencer2011-10-171-1/+0
| | | | llvm-svn: 142204
* svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cppDevang Patel2011-10-172-220/+2
| | | | | | There is no reason to have simple IR level pass in lib/Target. llvm-svn: 142200
* Instructions for Book E PPC should be word aligned, set function alignment ↵Hal Finkel2011-10-171-3/+10
| | | | | | to reflect this llvm-svn: 142194
* Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means ↵Craig Topper2011-10-172-24/+19
| | | | | | that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147. llvm-svn: 142177
* Add comment explaining that the order of processing doesn't matter here.Bill Wendling2011-10-171-0/+1
| | | | llvm-svn: 142176
* Add PPC 440 scheduler and some associated tests (new files)Hal Finkel2011-10-171-0/+568
| | | | llvm-svn: 142171
* Add PPC 440 scheduler and some associated testsHal Finkel2011-10-179-2/+53
| | | | llvm-svn: 142170
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-165-13/+42
| | | | llvm-svn: 142141
* Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing.Benjamin Kramer2011-10-161-9/+14
| | | | | | | | <stdin>:1:12: error: register %rax is only available in 64-bit mode incl %rax ^~~~ llvm-svn: 142137
* X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and ↵Benjamin Kramer2011-10-161-3/+4
| | | | | | | | | | print ranges for invalid operands. <stdin>:1:4: error: invalid instruction mnemonic 'abc' abc incl %edi ^~~ llvm-svn: 142135
* Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there wasNadav Rotem2011-10-161-3/+5
| | | | | | no pattern. llvm-svn: 142130
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-167-50/+56
| | | | llvm-svn: 142122
* Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, ↵Craig Topper2011-10-162-12/+25
| | | | | | VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. llvm-svn: 142117
* Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.Cameron Zwarich2011-10-161-1/+3
| | | | | | | These missing flags show up as errors when running -verify-coalescing on test-suite. llvm-svn: 142111
* Fix an obvious typo found when looking at nearby code.Cameron Zwarich2011-10-161-1/+1
| | | | llvm-svn: 142110
* Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang ↵Chris Lattner2011-10-161-6/+13
| | | | | | | | | | | | | | | does. Enhance the X86 asmparser to produce ranges in the one case that was annoying me, for example: test.s:10:15: error: invalid operand for instruction movl 0(%rax), 0(%edx) ^~~~~~~ It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use ranges where appropriate if someone is interested. llvm-svn: 142106
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper2011-10-163-18/+54
| | | | | | 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
* Add X86 feature detection support for BMI instructions. Added new cpuid ↵Craig Topper2011-10-163-18/+107
| | | | | | function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. llvm-svn: 142089
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper2011-10-153-17/+46
| | | | | | because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
* The CELL backend cannot select patterns for vector trunc-store and shl on ↵Nadav Rotem2011-10-151-0/+9
| | | | | | v2i64; CellSPU/shift_ops.ll fails when promoting elements. llvm-svn: 142081
* ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when ↵Nadav Rotem2011-10-151-0/+2
| | | | | | promoting elements. llvm-svn: 142080
* SmallVector -> arrayBenjamin Kramer2011-10-151-3/+3
| | | | llvm-svn: 142073
* Mark tADDrSPi as having side effects again.Jakob Stoklund Olesen2011-10-151-3/+3
| | | | | | | | | | | It really doesn't, but when r141929 removed the hasSideEffects flag from this instruction, it caused miscompilations. I am guessing that it got moved across a stack pointer update. Also clear isRematerializable after checking that this instruction is in fact never rematerialized in the nightly test suite. llvm-svn: 142030
* Thumb1 does not support dynamic stack realignment.Chad Rosier2011-10-151-0/+5
| | | | | | | | | | | rdar://10288916 is tracking this fix. In the past, instcombine and other passes were promoting alloca alignment past the natural alignment, resulting in dynamic stack realignment. Lang's work now prevents this from happening (LLVM commit r141599). Now that this really shouldn't happen report a fatal error rather than silently generate bad code. llvm-svn: 142028
* Mark registers as DEAD because they're really just clobbers.Bill Wendling2011-10-151-1/+1
| | | | llvm-svn: 142027
* Add missing correctness check to ARMTargetLowering::ReconstructShuffle. ↵Eli Friedman2011-10-141-0/+8
| | | | | | Fixes PR11129. llvm-svn: 142022
* Make sure that the register is in the register class before adding it as a ↵Bill Wendling2011-10-141-1/+3
| | | | | | machine op. llvm-svn: 142021
* Mark the invoke call instruction as implicitly defining the callee-saved ↵Bill Wendling2011-10-141-2/+31
| | | | | | | | | | registers. The callee-saved registers cannot be live across an invoke call because the control flow may continue along the exceptional edge. When this happens, all of the callee-saved registers are no longer valid. llvm-svn: 142018
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