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* Test commit.Jingyue Wu2014-05-231-1/+1
| | | | | | The keyword "virtual" is not necessary. llvm-svn: 209501
* [ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD ↵Jiangning Liu2014-05-231-15/+14
| | | | | | with swapped input vectors. llvm-svn: 209495
* R600: Add definition for flat address space ID.Matt Arsenault2014-05-222-4/+5
| | | | | | | | Use 4 since that's probably what it will be for spir. Move ADDRESS_NONE to the end to keep the constant_buffer_* values unchanged, since apparently a bunch of r600 tests use those directly. llvm-svn: 209463
* R600: Try to convert BFE back to standard bit ops when possible.Matt Arsenault2014-05-221-0/+21
| | | | | | | This allows existing DAG combines to work on them, and then we can re-match to BFE if necessary during instruction selection. llvm-svn: 209462
* R600: Add dag combine for BFEMatt Arsenault2014-05-223-2/+78
| | | | llvm-svn: 209461
* R600: Implement ComputeNumSignBitsForTargetNode for BFEMatt Arsenault2014-05-222-0/+30
| | | | llvm-svn: 209460
* R600: Implement computeMaskedBitsForTargetNode for BFEMatt Arsenault2014-05-221-1/+29
| | | | llvm-svn: 209459
* R600: Expand mul24 for GPUs without itMatt Arsenault2014-05-224-13/+25
| | | | llvm-svn: 209458
* R600: Expand mad24 for GPUs without itMatt Arsenault2014-05-224-1/+24
| | | | llvm-svn: 209457
* R600: Add intrinsics for mad24Matt Arsenault2014-05-227-3/+41
| | | | llvm-svn: 209456
* R600/SI: Move instruction pattern to instruction definitionMatt Arsenault2014-05-221-6/+3
| | | | llvm-svn: 209454
* [X86] Improve the lowering of BITCAST from MVT::f64 to MVT::v4i16/MVT::v8i8.Andrea Di Biagio2014-05-221-18/+38
| | | | | | | | | | | | | This patch teaches the x86 backend how to efficiently lower ISD::BITCAST dag nodes from MVT::f64 to MVT::v4i16 (and vice versa), and from MVT::f64 to MVT::v8i8 (and vice versa). This patch extends the logic from revision 208107 to also handle MVT::v4i16 and MVT::v8i8. Also, this patch correctly propagates Undef values when performing the widening of a vector (example: when widening from v2i32 to v4i32, the upper 64bits of the resulting vector are 'undef'). llvm-svn: 209451
* ARM64: remove '#' from annotation of add/sub immediateTim Northover2014-05-221-1/+1
| | | | | | | The full string used to be "// =#12" for example, which looks too busy. llvm-svn: 209443
* Segmented stacks: omit __morestack call when there's no frame.Tim Northover2014-05-222-7/+15
| | | | | | Patch by Florian Zeitz llvm-svn: 209436
* ARM64: these work tooTim Northover2014-05-221-2/+0
| | | | llvm-svn: 209430
* Yes they doTim Northover2014-05-221-1/+0
| | | | llvm-svn: 209429
* ARM64: model pre/post-indexed operations properly.Tim Northover2014-05-229-336/+241
| | | | | | | | | | We should be keeping track of the writeback on these instructions, otherwise we're relying on LLVM's stupidity for correct code. Fortunately, the MC layer can now handle all required constraints, which means we can get rid of the CodeGen only PseudoInsts too. llvm-svn: 209426
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-2211-2570/+2456
| | | | | | | | | | | | | | | | | | | This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
* [mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-05-222-2/+14
| | | | | | | | | | | | Summary: Depends on D3787. Tablegen will raise an assertion without it. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3842 llvm-svn: 209419
* [mips][mips64r6] Test that paired single instructions are invalidDaniel Sanders2014-05-221-1/+0
| | | | | | | | | | | | | | Summary: These emit the 'unknown instruction' instead of the correct error because they have not been implemented in LLVM for any MIPS ISA. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3841 llvm-svn: 209418
* [mips][mips64r6] Add b[on]vcDaniel Sanders2014-05-224-50/+353
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
* ARM64: assert if we see i64 -> i64 extend in the DAG.Tim Northover2014-05-221-4/+2
| | | | | | | | Should be no change in behaviour, but it makes the intended functionality a bit clearer and means we only have to reason about real extend operations. llvm-svn: 209409
* ARM: introduce llvm.arm.undefined intrinsicSaleem Abdulrasool2014-05-223-5/+5
| | | | | | | | | | | | This intrinsic permits the emission of platform specific undefined sequences. ARM has reserved the 0xde opcode which takes a single integer parameter (ignored by the CPU). This permits the operating system to implement custom behaviour on this trap. The llvm.arm.undefined intrinsic is meant to provide a means for generating the target specific behaviour from the frontend. This is particularly useful for Windows on ARM which has made use of a series of these special opcodes. llvm-svn: 209390
* R600/SI: Match fp_to_uint / uint_to_fp for f64Matt Arsenault2014-05-221-2/+7
| | | | llvm-svn: 209388
* Override runOnMachineFunction for ARMISelDAGToDAG so that we canEric Christopher2014-05-221-0/+7
| | | | | | reset the subtarget on each function. llvm-svn: 209386
* Override runOnMachineFunction for X86ISelDAGToDAG so that we canEric Christopher2014-05-221-0/+7
| | | | | | reset the subtarget on each function. llvm-svn: 209384
* Avoid using subtarget features when adding X86 specific passes toEric Christopher2014-05-225-14/+17
| | | | | | the pass pipeline. llvm-svn: 209382
* Remove extra local variable.Eric Christopher2014-05-221-2/+1
| | | | llvm-svn: 209381
* Rename createGlobalBaseRegPass -> createX86GlobalBaseRegPass to makeEric Christopher2014-05-223-4/+4
| | | | | | it obvious that it's a target specific pass. llvm-svn: 209380
* Fix typo.Eric Christopher2014-05-225-5/+5
| | | | llvm-svn: 209377
* Avoid using subtarget features when initializing the pass pipelineEric Christopher2014-05-222-12/+17
| | | | | | on PPC. llvm-svn: 209376
* Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.Eric Christopher2014-05-225-47/+47
| | | | | | | This required updating the generated functions and TD file accordingly to be pointers rather than const references. llvm-svn: 209375
* Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.Eric Christopher2014-05-221-1/+2
| | | | llvm-svn: 209374
* Sort includes.Eric Christopher2014-05-221-1/+1
| | | | llvm-svn: 209373
* Fix compilation issues.Eric Christopher2014-05-212-3/+4
| | | | llvm-svn: 209342
* Make early if conversion dependent upon the subtarget and addEric Christopher2014-05-218-23/+31
| | | | | | | a subtarget hook to enable. Unconditionally add to the pass pipeline for targets that might want to use it. No functional change. llvm-svn: 209340
* MC: correct IMAGE_REL_ARM_MOV32T relocation emissionSaleem Abdulrasool2014-05-212-6/+7
| | | | | | | | | | | | This corrects the emission of IMAGE_REL_ARM_MOV32T relocations. Previously, we were avoiding the high portion of the relocation too early. If there was a section-relative relocation with an offset greater than 16-bits (65535), you would end up truncating the high order bits of the offset. Allow the current relocation representation to flow through out the MC layer to the object writer. Use the new ability to restrict recorded relocations to avoid emitting the relocation into the final object. llvm-svn: 209337
* R600: Add comment describing problems with LowerConstantInitializerMatt Arsenault2014-05-211-0/+10
| | | | llvm-svn: 209333
* R600: Partially fix constant initializers for structs and vectors.Matt Arsenault2014-05-211-6/+33
| | | | | | | This should extend the current workaround to work with structs that only contain legal, scalar types. llvm-svn: 209331
* Remove getTargetLowering from TargetPassConfig as the target loweringEric Christopher2014-05-212-7/+10
| | | | | | can change depending upon subtarget/subtarget features for a function. llvm-svn: 209329
* Remove unused member variable from hexagon pass.Eric Christopher2014-05-211-4/+3
| | | | llvm-svn: 209328
* [X86] Fix a bug in the lowering of BLENDI introduced in r209043.Quentin Colombet2014-05-211-3/+7
| | | | | | | | | | | | | | | | | | | ISD::VSELECT mask uses 1 to identify the first argument and 0 to identify the second argument. On the other hand, BLENDI uses 0 to identify the first argument and 1 to identify the second argument. Fix the generation of the blend mask to account for this difference. The bug did not show up with r209043, because we were not checking for the actual arguments of the blend instruction! This commit also fixes the test cases. Note: The same mask works for the BLENDr variant because the arguments are swapped during instruction selection (see the BLENDXXrr patterns). <rdar://problem/16975435> llvm-svn: 209324
* Use cast<> instead of unchecked dyn_castMatt Arsenault2014-05-211-1/+1
| | | | llvm-svn: 209310
* [mips][mips64r6] Add bc[12](eq|ne)zDaniel Sanders2014-05-213-4/+75
| | | | | | | | | | | | Summary: Depends on D3691 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3760 llvm-svn: 209292
* [asan] Fix x86-32 asm instrumentation to preserve flags.Evgeniy Stepanov2014-05-211-2/+1
| | | | | | Patch by Yuri Gorshenin. llvm-svn: 209280
* ARM: correct bundle generation for MOV32T relocationsSaleem Abdulrasool2014-05-211-7/+3
| | | | | | | | | | | | | | | | | | | | | | | Although the previous code would construct a bundle and add the correct elements to it, it would not finalise the bundle. This resulted in the InternalRead markers not being added to the MachineOperands nor, more importantly, the externally visible defs to the bundle itself. So, although the bundle was not exposing the def, the generated code would be correct because there was no optimisations being performed. When optimisations were enabled, the post register allocator would kick in, and the hazard recognizer would reorder operations around the load which would define the value being operated upon. Rather than manually constructing the bundle, simply construct and finalise the bundle via the finaliseBundle call after both MIs have been emitted. This improves the code generation with optimisations where IMAGE_REL_ARM_MOV32T relocations are emitted. The changes to the other tests are the result of the bundle generation preventing the scheduler from hoisting the moves across the loads. The net effect of the generated code is equivalent, but, is much more identical to what is actually being lowered. llvm-svn: 209267
* Move the verbose asm option to be part of the options struct andEric Christopher2014-05-201-11/+3
| | | | | | set appropriately. llvm-svn: 209258
* [ARM64] PR19792: Fix cycle in DAG after performPostLD1CombineAdam Nemet2014-05-201-1/+6
| | | | | | | | | | | | | | | | | | | Povray and dealII currently assert with "Overran sorted position" in AssignTopologicalOrder. The problem is that performPostLD1Combine can introduce cycles. Consider: (insert_vector_elt (INSERT_SUBREG undef, (load (add %vreg0, Constant<8>), undef), <= A TargetConstant<2>), (load %vreg0, undef), <= B Constant<1>) This is turned into a LD1LANEpost node. However the address in A is not a valid user of the post-incremented address of B in LD1LANEpost. llvm-svn: 209242
* Move the function and data section flags into the options struct andEric Christopher2014-05-201-15/+6
| | | | | | | | | | make the functions to set them non-static. Move and rename the llvm specific backend options to avoid conflicting with the clang option. Paired with a backend commit to update. llvm-svn: 209238
* [PowerPC] PR19796: Also match ISD::TargetConstant in isIntS16ImmediateAdam Nemet2014-05-201-1/+1
| | | | | | | | | | | | | The SplitIndexingFromLoad changes exposed a latent isel bug in the PowerPC64 backend. We matched an immediate offset with STWX8 even though it only supports register offset. The culprit is the complex-pattern predicate, SelectAddrIdx, which decides that if the offset is not ISD::Constant it must be a register. Many thanks to Bill Schmidt for testing this. llvm-svn: 209219
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