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* trailing whitespaceJim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117740
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-293-3/+3
| | | | | | encoder functions. llvm-svn: 117738
* Fix fpscr <-> GPR latency info.Evan Cheng2010-10-293-4/+12
| | | | llvm-svn: 117737
* add FIXMEJim Grosbach2010-10-291-0/+5
| | | | llvm-svn: 117718
* Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it inJim Grosbach2010-10-294-45/+32
| | | | | | the ARMExpandPseudos pass rather than during the asm lowering. llvm-svn: 117714
* Handle comparison values we already have - this fixes the consumer-typesetEric Christopher2010-10-291-4/+65
| | | | | | failure for llvm-gcc on arm fast isel. llvm-svn: 117710
* ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need toJim Grosbach2010-10-291-55/+0
| | | | | | handle it in the asm lowering. llvm-svn: 117707
* Fix typo.Jim Grosbach2010-10-291-1/+1
| | | | llvm-svn: 117703
* ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj ↵Jim Grosbach2010-10-292-20/+25
| | | | | | pseudos and a FIXME for TLS. llvm-svn: 117702
* ARM mode LDREX*/STREX* binary encodings.Jim Grosbach2010-10-292-18/+28
| | | | llvm-svn: 117695
* Encoding information for ARM conditional move instructions.Jim Grosbach2010-10-291-19/+35
| | | | llvm-svn: 117687
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-291-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | operand and one of them has a single use that is a live out copy, favor the one that is live out. Otherwise it will be difficult to eliminate the copy if the instruction is a loop induction variable update. e.g. BB: sub r1, r3, #1 str r0, [r2, r3] mov r3, r1 cmp bne BB => BB: str r0, [r2, r3] sub r3, r3, #1 cmp bne BB This fixed the recent 256.bzip2 regression. llvm-svn: 117675
* - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.Evan Cheng2010-10-291-3/+7
| | | | | | - Compute CopyToReg use operand latency correctly. llvm-svn: 117674
* Handle ARM addrmode5 instructions with an offset.Jim Grosbach2010-10-291-9/+24
| | | | llvm-svn: 117672
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-2917-24/+393
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* Revert 117660. Apparently it's not as trivial as that...Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117663
* ARM addrmode5 instructions have neither writeback nor post-indexed modes.Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117660
* Trailing whitespace.Jim Grosbach2010-10-291-30/+30
| | | | llvm-svn: 117651
* ARMAsmParser: Plug a memory leak.Benjamin Kramer2010-10-291-2/+3
| | | | llvm-svn: 117648
* Add an unreachable to silence warning - the switch is actuallyEric Christopher2010-10-291-0/+2
| | | | | | fully enumerated. llvm-svn: 117647
* add simple support for addrmode5 operands, allowingChris Lattner2010-10-292-10/+31
| | | | | | | vldr.64 to work. I have no idea if this is fully right, but it is in the right direction. llvm-svn: 117626
* give better error diagnostics, for example:Chris Lattner2010-10-281-5/+20
| | | | | | | | | | | | | | t.s:1:14: error: invalid operand for instruction vldr.64 d17, [r0] ^ instead of: t.s:1:1: error: unrecognized instruction vldr.64 d17, [r0] ^ llvm-svn: 117611
* hook up getOpcodeName for ARM so that "llc -show-mc-inst" includesChris Lattner2010-10-282-0/+9
| | | | | | | | | | | | | | | the opcode string in the inst dump, e.g.: vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec] @ <MCInst #989 VMOVRRD @ <MCOperand Reg:68> @ <MCOperand Reg:69> @ <MCOperand Reg:19> @ <MCOperand Imm:14> @ <MCOperand Reg:0>> The "VMOVRRD" is new. llvm-svn: 117609
* move a method out of line.Chris Lattner2010-10-281-13/+20
| | | | llvm-svn: 117605
* remove the rest of hte owningptr's, no functionality change.Chris Lattner2010-10-281-57/+59
| | | | llvm-svn: 117603
* Reduce malloc thrashing.Benjamin Kramer2010-10-281-1/+1
| | | | llvm-svn: 117572
* PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.Jim Grosbach2010-10-284-20/+44
| | | | llvm-svn: 117571
* rearrange ParseRegisterList.Chris Lattner2010-10-281-16/+30
| | | | llvm-svn: 117560
* refactor some code to simplify it, eliminating some owningptr's.Chris Lattner2010-10-281-65/+60
| | | | llvm-svn: 117559
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-284-23/+85
| | | | llvm-svn: 117531
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ↵Evan Cheng2010-10-284-85/+23
| | | | | | to fail. Ugh. llvm-svn: 117520
* - Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng2010-10-284-23/+85
| | | | | | | | | | - For now, loads of [r, r] addressing mode is the same as the [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should identify the former case and reduce the output latency by 1. - Also identify [r, r << 2] case. This special form of shifter addressing mode is "free". llvm-svn: 117519
* Fix pastos in handling of AVX cvttsd2si, PR8491.Dale Johannesen2010-10-281-4/+4
| | | | | | | Bruno, please review, but I'm pretty sure this is right. Patch by Alex Mac! llvm-svn: 117514
* Add correct NEON encodings for vtbl and vtbx.Owen Anderson2010-10-281-29/+29
| | | | llvm-svn: 117513
* Add correct NEON encodings for vext, vtrn, vuzp, and vzip.Owen Anderson2010-10-271-2/+8
| | | | llvm-svn: 117512
* Fix compiler warnings about signed/unsigned comparisons.Bob Wilson2010-10-271-2/+2
| | | | llvm-svn: 117511
* Shifter ops are not always free. Do not fold them (especially to formEvan Cheng2010-10-272-16/+119
| | | | | | | complex load / store addressing mode) when they have higher cost and when they have more than one use. llvm-svn: 117509
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-279-101/+94
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
* Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson2010-10-274-6/+16
| | | | | | | | encoding for specifying fractional bits for fixed point conversions. llvm-svn: 117501
* Trailing whitespaceJim Grosbach2010-10-271-17/+17
| | | | llvm-svn: 117496
* Provide correct encodings for the get_lane and set_lane variants of vmov.Owen Anderson2010-10-272-41/+64
| | | | llvm-svn: 117495
* Added the x86 instruction ud2b (2nd official undefined instruction).Kevin Enderby2010-10-271-1/+3
| | | | llvm-svn: 117485
* JIT imm12 encoding for constant pool entry references.Jim Grosbach2010-10-271-0/+4
| | | | llvm-svn: 117483
* SelectionDAG shuffle nodes do not allow operands with different numbers ofBob Wilson2010-10-271-0/+55
| | | | | | | | | | | | | | | | | | | elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. llvm-svn: 117482
* ARM JIT fix for LDRi12 and company.Jim Grosbach2010-10-272-4/+18
| | | | llvm-svn: 117478
* Provide correct NEON encodings for vdup.Owen Anderson2010-10-272-8/+42
| | | | llvm-svn: 117475
* x86-Win32: Switch ftol2 calling convention from stdcall to C.Michael J. Spencer2010-10-271-2/+2
| | | | llvm-svn: 117474
* The new LDR* instruction patterns should handle the necessary encoding ofJim Grosbach2010-10-271-0/+7
| | | | | | | operands in the TableGen'erated bits, so we don't need to do the additional magic explicitly. llvm-svn: 117461
* Add correct NEON encodings for vsli and vsri.Owen Anderson2010-10-271-8/+8
| | | | llvm-svn: 117459
* Add correct NEON encodings for vsra and vrsra.Owen Anderson2010-10-271-10/+10
| | | | llvm-svn: 117458
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