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* [X86][MMX] Prevent MMX_MOVD64rm foldingBruno Cardoso Lopes2015-02-251-1/+0
| | | | | | | | | | | | | | | MMX_MOVD64rm zero-extends i32 load results into i64 registers. The peephole optimizer will try to fold it in other MMX foldable instructions, the wrong thing to do, since there's no MMX memory instruction that loads from i32 and does implict zero extension. Remove 'canFoldAsLoad' from MOVD64rm in order to prevent such folding. The current MMX tests already test this, but since there are no MMX instructions in the foldable tables yet, this did not trigger. This commit prepares the addition of those instructions. llvm-svn: 230498
* Improve handling of stack accesses in Thumb-1Renato Golin2015-02-254-12/+57
| | | | | | | | | | | | | | | | | Thumb-1 only allows SP-based LDR and STR to be word-sized, and SP-base LDR, STR, and ADD only allow offsets that are a multiple of 4. Make some changes to better make use of these instructions: * Use word loads for anyext byte and halfword loads from the stack. * Enforce 4-byte alignment on objects accessed in this way, to ensure that the offset is valid. * Do the same for objects whose frame index is used, in order to avoid having to use more than one ADD to generate the frame index. * Correct how many bits of offset we think AddrModeT1_s has. Patch by John Brawn. llvm-svn: 230496
* Silencing a "result of 32-bit shift implicitly converted to 64 bits (was ↵Aaron Ballman2015-02-251-1/+1
| | | | | | 64-bit shift intended?)" warning in MSVC; NFC. llvm-svn: 230489
* Silencing a -Wsign-compare warning triggered in MSVC; NFC.Aaron Ballman2015-02-251-1/+1
| | | | llvm-svn: 230488
* AVX-512: Gather and Scatter patternsElena Demikhovsky2015-02-253-44/+108
| | | | | | | | | | | | | | | Gather and scatter instructions additionally write to one of the source operands - mask register. In this case Gather has 2 destination values - the loaded value and the mask. Till now we did not support code gen pattern for gather - the instruction was generated from intrinsic only and machine node was hardcoded. When we introduce the masked_gather node, we need to select instruction automatically, in the standard way. I added a flag "hasTwoExplicitDefs" that allows to handle 2 destination operands. (Some code in the X86InstrFragmentsSIMD.td is commented out, just to split one big patch in many small patches) llvm-svn: 230471
* [PowerPC] Add support for the QPX vector instruction setHal Finkel2015-02-2519-67/+2675
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the QPX vector instruction set, which is used by the enhanced A2 cores on the IBM BG/Q supercomputers. QPX vectors are 256 bytes wide, holding 4 double-precision floating-point values. Boolean values, modeled here as <4 x i1> are actually also represented as floating-point values (essentially { -1, 1 } for { false, true }). QPX shares many features with Altivec and VSX, but is distinct from both of them. One major difference is that, instead of adding completely-separate vector registers, QPX vector registers are extensions of the scalar floating-point registers (lane 0 is the corresponding scalar floating-point value). The operations supported on QPX vectors mirrors that supported on the scalar floating-point values (with some additional ones for permutations and logical/comparison operations). I've been maintaining this support out-of-tree, as part of the bgclang project, for several years. This is not the entire bgclang patch set, but is most of the subset that can be cleanly integrated into LLVM proper at this time. Adding this to the LLVM backend is part of my efforts to rebase bgclang to the current LLVM trunk, but is independently useful (especially for codes that use LLVM as a JIT in library form). The assembler/disassembler test coverage is complete. The CodeGen test coverage is not, but I've included some tests, and more will be added as follow-up work. llvm-svn: 230413
* Rename UpdateRegAllocHint to match style guidelines.Eric Christopher2015-02-242-2/+2
| | | | llvm-svn: 230357
* AArch64: Relax assert about large shift sizes.Matthias Braun2015-02-241-3/+9
| | | | | | | | | | The reason why these large shift sizes happen is because OpaqueConstants currently inhibit alot of DAG combining, but that has to be addressed in another commit (like the proposal in D6946). Differential Revision: http://reviews.llvm.org/D6940 llvm-svn: 230355
* R600/SI: Remove isel mubuf legalizationTom Stellard2015-02-242-130/+0
| | | | | | | We legalize mubuf instructions post-instruction selection, so this code is no longer needed. llvm-svn: 230352
* ARM: treat [N x i32] and [N x i64] as AAPCS composite typesTim Northover2015-02-243-61/+100
| | | | | | | | | | | The logic is almost there already, with our special homogeneous aggregate handling. Tweaking it like this allows front-ends to emit AAPCS compliant code without ever having to count registers or add discarded padding arguments. Only arrays of i32 and i64 are needed to model AAPCS rules, but I decided to apply the logic to all integer arrays for more consistency. llvm-svn: 230348
* simplify control flow; NFCSanjay Patel2015-02-241-8/+9
| | | | llvm-svn: 230342
* [x32] Mark RBX as reserved when EBX is the base pointer.Michael Kuperstein2015-02-241-1/+3
| | | | | | This should have gone into r230334. llvm-svn: 230339
* fix typo in comment; NFCSanjay Patel2015-02-241-1/+1
| | | | llvm-svn: 230338
* [x32] x32 should use ebx as the base pointer.Michael Kuperstein2015-02-241-8/+9
| | | | | | This fixes the original issue in PR22655, but not the secondary one. llvm-svn: 230334
* [mips] Reformat some TableGen definitions. NFC.Toma Tabacu2015-02-242-14/+18
| | | | | | | | | | | | | | Summary: Separated some instruction and pseudo-instruction definitions from InstAlias definitions, added banner for pseudo-instructions and removed a redundant whitespace from a pseudo-instruction definition. No functional change. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7552 llvm-svn: 230327
* [X86] Remove the AbsMem32 type from the assembly parser. Only really need ↵Craig Topper2015-02-242-12/+2
| | | | | | the 16-bit version which will automatically get prioritized over AbsMem. llvm-svn: 230313
* Beginning of alloca implementation for Mips fast-iselReed Kotler2015-02-241-20/+139
| | | | | | | | | | | | | | | | Summary: Begin to add various address modes; including alloca. Test Plan: Make sure there are no regressions in test-suite at O0/02 in mips32r1/r2 Reviewers: dsanders Reviewed By: dsanders Subscribers: echristo, rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6426 llvm-svn: 230300
* Fix handling of negative offsets for AddrModeT2_i8s4 in rewriteT2FrameIndex.Bob Wilson2015-02-241-5/+2
| | | | | | | | | | | | | | This is a follow up to r230233 to fix something that I noticed by inspection. The AddrModeT2_i8s4 addressing mode does not support negative offsets. I spent a good chunk of the day trying to come up with a testcase for this but was not successful. This addressing mode is used to spill and restore GPRPair registers in Thumb2 code and that does not happen often. We also make very limited used of negative offsets when lowering frame indexes. I am going ahead with the change anyway, because I am pretty confident that it is correct. I also added a missing assertion to check that the low bits of the scaled offset are zero. llvm-svn: 230297
* X86: Only use 'lea' in Win64 epilogues if a frame pointer existsDavid Majnemer2015-02-241-7/+21
| | | | | | | We can only use 'add' in epilogues, 'lea' is not permitted unless we've established a frame pointer in the prologue. llvm-svn: 230286
* X86: Use a smaller 'mov' instruction for stack probe callsDavid Majnemer2015-02-231-3/+13
| | | | | | | | | | | | | Prologue emission, in some cases, requires calls to a stack probe helper function. The amount of stack to probe is passed as a register argument in the Win64 ABI but the instruction sequence used is pessimistic: it assumes that the number of bytes to probe is greater than 4 GB. Instead, select a more appropriate opcode depending on the number of bytes we are going to probe. llvm-svn: 230270
* X86: Use 'mov' instead of 'lea' in Win64 SEH prologues when possibleDavid Majnemer2015-02-231-2/+5
| | | | | | | 'mov' and 'lea' are equivalent when the displacement applied with 'lea' is zero. However, 'mov' should encode smaller. llvm-svn: 230269
* X86: Explain why we cannot use a 'mov' in a Win64 epilogueDavid Majnemer2015-02-231-0/+6
| | | | llvm-svn: 230268
* X86: Consistently use 'epilogue' instead of 'epilog'David Majnemer2015-02-231-1/+1
| | | | llvm-svn: 230267
* [AsmPrinter] Access pointers to globals via pcrel GOT entriesBruno Cardoso Lopes2015-02-232-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Front-ends could use global unnamed_addr to hold pointers to other symbols, like @gotequivalent below: @foo = global i32 42 @gotequivalent = private unnamed_addr constant i32* @foo @delta = global i32 trunc (i64 sub (i64 ptrtoint (i32** @gotequivalent to i64), i64 ptrtoint (i32* @delta to i64)) to i32) The global @delta holds a data "PC"-relative offset to @gotequivalent, an unnamed pointer to @foo. The darwin/x86-64 assembly output for this follows: .globl _foo _foo: .long 42 .globl _gotequivalent _gotequivalent: .quad _foo .globl _delta _delta: .long _gotequivalent-_delta Since unnamed_addr indicates that the address is not significant, only the content, we can optimize the case above by replacing pc-relative accesses to "GOT equivalent" globals, by a PC relative access to the GOT entry of the final symbol instead. Therefore, "delta" can contain a pc relative relocation to foo's GOT entry and we avoid the emission of "gotequivalent", yielding the assembly code below: .globl _foo _foo: .long 42 .globl _delta _delta: .long _foo@GOTPCREL+4 There are a couple of advantages of doing this: (1) Front-ends that need to emit a great deal of data to store pointers to external symbols could save space by not emitting such "got equivalent" globals and (2) IR constructs combined with this opt opens a way to represent GOT pcrel relocations by using the LLVM IR, which is something we previously had no way to express. Differential Revision: http://reviews.llvm.org/D6922 rdar://problem/18534217 llvm-svn: 230264
* Revert "[X86][MMX] Add MMX instructions to foldable tables"Bruno Cardoso Lopes2015-02-231-82/+0
| | | | | | This reverts commit r230226 since it breaks win buildbots. llvm-svn: 230248
* Rewrite the global merge pass to be subprogram agnostic for now.Eric Christopher2015-02-236-23/+10
| | | | | | | | | | | | | It was previously using the subtarget to get values for the global offset without actually checking each function as it was generating code. Go ahead and solidify the current behavior and make the existing FIXMEs more prominent. As a note the ARM backend previously had a thumb1 and non-thumb1 set of defaults. Only the former was tested so I've changed the behavior to only use that for now. llvm-svn: 230245
* Prevent hoisting fmul from THEN/ELSE to IF if there is fmsub/fmadd opportunity.Chad Rosier2015-02-232-0/+31
| | | | | | | | | | | This patch adds the isProfitableToHoist API. For AArch64, we want to prevent a fmul from being hoisted in cases where it is more profitable to form a fmsub/fmadd. Phabricator Review: http://reviews.llvm.org/D7299 Patch by Lawrence Hu <lawrence@codeaurora.org> llvm-svn: 230241
* [mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled.Daniel Sanders2015-02-232-5/+20
| | | | | | | | | | | | | | | | | | | Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
* Fix incorrect immediate size for AddrModeT2_i8s4 in rewriteT2FrameIndex.Bob Wilson2015-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The natural way to handle this addressing mode would be to say that it has 8 bits and gets scaled by 4, but since the MC layer is expecting the scaling to be already reflected in the immediate value, we have been setting the Scale to 1. That's fine, but then NumBits needs to be adjusted to reflect the effective increase in the range of the immediate. That adjustment was missing. The consequence is that the register scavenger can fail. The estimateRSStackSizeLimit() function in ARMFrameLowering.cpp correctly assumes that the AddrModeT2_i8s4 address mode can handle scaled offsets up to 1020. Under just the right circumstances, we fail to reserve space for the scavenger because it thinks that nothing will be needed. However, the overly pessimistic behavior in rewriteT2FrameIndex causes some frame indexes to be out of range and require scavenged registers, and so the scavenger asserts. Unfortunately I have not been able to come up with a testcase for this. I can only reproduce it on an internal branch where the frame layout and register allocation is slightly different than trunk. We really need a way to serialize MachineInstr-level IR to write reasonable tests for things like this. rdar://problem/19909005 llvm-svn: 230233
* [X86][MMX] Add MMX instructions to foldable tablesBruno Cardoso Lopes2015-02-231-0/+82
| | | | | | | | Teach the peephole optimizer to work with MMX instructions by adding entries into the foldable tables. This covers folding opportunities not handled during isel. llvm-svn: 230226
* [X86][MMX] Support folding loads in psll, psrl and psra intrinsicsBruno Cardoso Lopes2015-02-232-0/+21
| | | | llvm-svn: 230225
* AVX-512: recommitted 229837 + bugfix + testElena Demikhovsky2015-02-235-47/+87
| | | | llvm-svn: 230223
* restructured X86 scalar unary operation templatesElena Demikhovsky2015-02-231-164/+118
| | | | | | | I made the templates general, no need to define pattern separately for each instruction/intrinsic. Now only need to add r_Int pattern for AVX. llvm-svn: 230221
* Fix a warning on HexagonMCCodeEmitter::MCII. [-Wunused-private-field]NAKAMURA Takumi2015-02-221-0/+1
| | | | llvm-svn: 230170
* [X86] Add some missing redundant MMX and SSE encodings for disassembler.Craig Topper2015-02-222-0/+28
| | | | llvm-svn: 230165
* R600/SI: Use v_madmk_f32Matt Arsenault2015-02-211-4/+51
| | | | llvm-svn: 230149
* R600/SI: Try to use v_madak_f32Matt Arsenault2015-02-212-0/+81
| | | | | | | This is a code size optimization when the constant only has one use. llvm-svn: 230148
* R600/SI: Don't crash when getting immediate operand sizeMatt Arsenault2015-02-211-0/+7
| | | | llvm-svn: 230147
* R600/SI: Fix mad*k definitionsMatt Arsenault2015-02-214-2/+40
| | | | llvm-svn: 230146
* Remove dead prototype.Benjamin Kramer2015-02-211-1/+0
| | | | llvm-svn: 230137
* X86: Remove custom lowering of SIGN_EXTEND_INREGBenjamin Kramer2015-02-211-68/+0
| | | | | | | This was just replicating logic from the legalizer. Covered by existing tests. llvm-svn: 230136
* Remove obsolete comment.Eric Christopher2015-02-211-5/+0
| | | | llvm-svn: 230134
* Have the MipsAsmPrinter fp stub emission code take a customEric Christopher2015-02-212-43/+59
| | | | | | | MCSubtargetInfo as the MachineFunction has gone away and we need to emit code at the module level. llvm-svn: 230133
* Turn an if+llvm_unreachable into an assert and reword comment.Eric Christopher2015-02-211-7/+4
| | | | llvm-svn: 230132
* Endianness can be gotten from the DataLayout which we alreadyEric Christopher2015-02-211-1/+1
| | | | | | have. Also, the subtarget is invalid at this point. llvm-svn: 230131
* X86: Call __main using the SelectionDAGDavid Majnemer2015-02-211-9/+13
| | | | | | | | Synthesizing a call directly using the MI layer would confuse the frame lowering code. This is problematic as frame lowering is highly sensitive the particularities of calls, etc. llvm-svn: 230129
* CodeGen: convert CCState interface to using ArrayRefsTim Northover2015-02-2112-58/+46
| | | | | | | | | | | Everyone except R600 was manually passing the length of a static array at each callsite, calculated in a variety of interesting ways. Far easier to let ArrayRef handle that. There should be no functional change, but out of tree targets may have to tweak their calls as with these examples. llvm-svn: 230118
* Win64: Stack alignment constraints aren't applied during SET_FPREGDavid Majnemer2015-02-211-36/+25
| | | | | | | | | | Stack realignment occurs after the prolog, not during, for Win64. Because of this, don't factor in the maximum stack alignment when establishing a frame pointer. This fixes PR22572. llvm-svn: 230113
* X86: Remove pre-2010 dead code in mergeSPUpdatesDownReid Kleckner2015-02-201-36/+0
| | | | llvm-svn: 230075
* LowerScalarImmediateShift - Merged v16i8 and v32i8 shift lowering. NFC.Simon Pilgrim2015-02-201-60/+13
| | | | llvm-svn: 230074
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