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* [DAG][ARM] Revert "Reenable post-legalize store merge"Nirav Dave2017-12-011-0/+3
| | | | | | due to failures in AArch and ARM code gen. llvm-svn: 319587
* [X86][AVX512] Tag subvector extract/insert instructions scheduler classesSimon Pilgrim2017-12-011-32/+65
| | | | llvm-svn: 319568
* Fix line endings. NFCI.Simon Pilgrim2017-12-011-10/+10
| | | | llvm-svn: 319559
* [X86][AVX512] Tag VPERM2I/VPERM2T instructions scheduler classSimon Pilgrim2017-12-011-48/+64
| | | | llvm-svn: 319558
* [X86][AVX512] Tag VFPCLASS instructions scheduler classSimon Pilgrim2017-12-011-26/+43
| | | | llvm-svn: 319554
* [X86][AVX512] Tag VPSHUFBITQMB instructions scheduler classSimon Pilgrim2017-12-011-9/+12
| | | | llvm-svn: 319553
* [X86][AVX512] Tag VPCOMRESS/VPEXPAND instructions scheduler classesSimon Pilgrim2017-12-011-39/+55
| | | | llvm-svn: 319551
* [ARM][DAG] Reenable post-legalize store mergeNirav Dave2017-12-011-3/+0
| | | | | | | | | | | | Summary: Reenable post-legalize stores with constant merging computation and cofrresponding test case. Reviewers: eastig, efriedma Subscribers: aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40701 llvm-svn: 319547
* [X86] Improvement in CodeGen instruction selection for LEAs.Jatin Bhateja2017-12-012-11/+563
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: 1/ Operand folding during complex pattern matching for LEAs has been extended, such that it promotes Scale to accommodate similar operand appearing in the DAG e.g. T1 = A + B T2 = T1 + 10 T3 = T2 + A For above DAG rooted at T3, X86AddressMode will now look like Base = B , Index = A , Scale = 2 , Disp = 10 2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs so that if there is an opportunity then complex LEAs (having 3 operands) could be factored out e.g. leal 1(%rax,%rcx,1), %rdx leal 1(%rax,%rcx,2), %rcx will be factored as following leal 1(%rax,%rcx,1), %rdx leal (%rdx,%rcx) , %edx 3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops, thus avoiding creation of any complex LEAs within a loop. 4/ Simplify LEA converts (lea (BASE,1,INDEX,0) --> add (BASE, INDEX) which offers better through put. PR32755 will be taken care of by this pathc. Previous patch revisions : r313343 , r314886 Reviewers: lsaba, RKSimon, craig.topper, qcolombet, jmolloy, jbhateja Reviewed By: lsaba, RKSimon, jbhateja Subscribers: jmolloy, spatel, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35014 llvm-svn: 319543
* [X86][AVX512] Tag vshift/vpermv/pshufd/pshufb instructions scheduler classesSimon Pilgrim2017-12-012-120/+158
| | | | llvm-svn: 319540
* Follow-up to r319434 to turn the pass on by defaultNemanja Ivanovic2017-12-011-1/+1
| | | | | | | Now that the patch has gone through the buildbot cycle, turn it on by default. llvm-svn: 319535
* [AMDGPU] SiFixSGPRCopies should not modify non-divergent PHIAlexander Timofeev2017-12-011-15/+64
| | | | | | Differential revision: https://reviews.llvm.org/D40556 llvm-svn: 319534
* GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUESVolkan Keles2017-12-013-0/+99
| | | | | | | | | | | | | | Summary: LegalizerInfo assumes all G_MERGE_VALUES and G_UNMERGE_VALUES instructions are legal, so it is not possible to legalize vector operations on illegal vector types. This patch fixes the problem by removing the related check and adding default actions for G_MERGE_VALUES and G_UNMERGE_VALUES. Reviewers: qcolombet, ab, dsanders, aditya_nandakumar, t.p.northover, kristof.beyls Reviewed By: dsanders Subscribers: rovka, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39823 llvm-svn: 319524
* [X86] Custom legalize v2i32 gathers via widening rather than promoting.Craig Topper2017-12-011-33/+57
| | | | | | | | The default legalization for v2i32 is promotion to v2i64. This results in a gather that reads 64-bit elements rather than 32. If one of the elements is near a page boundary this can cause an illegal access that can fault. We also miscalculate the scale for the gather which is an even worse problem, but we probably could have found a separate way to fix that. llvm-svn: 319521
* [X86] Add a DAG combine to simplify masks for AVX2 gather instructions.Craig Topper2017-12-011-0/+17
| | | | | | AVX2 gathers only use the upper bit of the mask allowing us to simplify sign_extend_inreg to a shift left. llvm-svn: 319514
* Mark all library options as hidden.Zachary Turner2017-12-012-7/+8
| | | | | | | | | | | | | | | | | These command line options are not intended for public use, and often don't even make sense in the context of a particular tool anyway. About 90% of them are already hidden, but when people add new options they forget to hide them, so if you were to make a brand new tool today, link against one of LLVM's libraries, and run tool -help you would get a bunch of junk that doesn't make sense for the tool you're writing. This patch hides these options. The real solution is to not have libraries defining command line options, but that's a much larger effort and not something I'm prepared to take on. Differential Revision: https://reviews.llvm.org/D40674 llvm-svn: 319505
* AMDGPU: Use carry-less adds in FI eliminationMatt Arsenault2017-11-302-9/+6
| | | | llvm-svn: 319501
* AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault2017-11-306-34/+118
| | | | llvm-svn: 319491
* XOR the frame pointer with the stack cookie when protecting the stackReid Kleckner2017-11-304-0/+41
| | | | | | | | | | | | Summary: This strengthens the guard and matches MSVC. Reviewers: hans, etienneb Subscribers: hiraditya, JDevlieghere, vlad.tsyrklevich, llvm-commits Differential Revision: https://reviews.llvm.org/D40622 llvm-svn: 319490
* [Hexagon] Implement HexagonSubtarget::useAA()Krzysztof Parzyszek2017-11-302-1/+14
| | | | llvm-svn: 319477
* [globalisel][tablegen] Add support for relative AtomicOrderingsDaniel Sanders2017-11-301-18/+16
| | | | | | | No test yet because the relevant rules are blocked on the atomic_load, and atomic_store nodes. llvm-svn: 319475
* [Hexagon] Solo instructions cannot be used with new value jumpsKrzysztof Parzyszek2017-11-301-0/+3
| | | | llvm-svn: 319470
* [X86] Promote i8 CTPOP to i32 instead of i16 when we have the POPCNT ↵Craig Topper2017-11-301-1/+1
| | | | | | | | instruction. The 32-bit version is shorter to encode and the zext we emit for the promotion is likely going to be a 32-bit zero extend anyway. llvm-svn: 319468
* [aarch64][globalisel] Legalize G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_*Daniel Sanders2017-11-301-1/+3
| | | | | | | | | | | G_ATOMICRMW_* is generally legal on AArch64. The exception is G_ATOMICRMW_NAND. G_ATOMIC_CMPXCHG_WITH_SUCCESS needs to be lowered to G_ATOMIC_CMPXCHG with an external comparison. Note that IRTranslator doesn't generate these instructions yet. llvm-svn: 319466
* [GlobalISel][IRTranslator] Fix crash during translation of zero sized ↵Amara Emerson2017-11-301-0/+2
| | | | | | | | | | | | loads/stores/args/returns. This fixes PR35358. rdar://35619533 Differential Revision: https://reviews.llvm.org/D40604 llvm-svn: 319465
* [WebAssembly] Revert r319186 "Support bitcasted function addresses with ↵Dan Gohman2017-11-301-0/+5
| | | | | | | | | | | varargs." The patch broke Emscripten's EM_ASM macros, which utiltize unprototyped functions. See https://bugs.llvm.org/show_bug.cgi?id=35385 for details. llvm-svn: 319452
* [CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih2017-11-303-15/+14
| | | | | | | | | | | | | | output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
* [PowerPC] Recommit r314244 with refactoring and off by defaultNemanja Ivanovic2017-11-301-0/+1236
| | | | | | | | | | | | | | | This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
* [X86][AVX512] Tag fcmp/ptest/ternlog instructions scheduler classesSimon Pilgrim2017-11-301-70/+90
| | | | llvm-svn: 319433
* [ARM GlobalISel] Bail out for byvalDiana Picus2017-11-301-1/+7
| | | | | | | Fallback if we have a byval parameter or argument since we don't support them yet. llvm-svn: 319428
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-3026-218/+218
| | | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
* [X86][AVX512] Tag binop/rounding/sae instructions scheduler classesSimon Pilgrim2017-11-301-124/+143
| | | | llvm-svn: 319424
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classesSimon Pilgrim2017-11-302-64/+100
| | | | llvm-svn: 319418
* [SystemZ] Bugfix in adjustSubwordCmp.Jonas Paulsson2017-11-301-4/+11
| | | | | | | | | | | | | | | | Csmith generated a program where a store after load to the same address did not get chained after the new load created during DAG legalizing, and so performed an illegal overwrite of the expected value. When the new zero-extending load is created, the chain users of the original load must be updated, which was not done previously. A similar case was also found and handled in lowerBITCAST. Review: Ulrich Weigand https://reviews.llvm.org/D40542 llvm-svn: 319409
* [X86] Optimize avx2 vgatherqps for v2f32 with v2i64 index type.Craig Topper2017-11-301-7/+12
| | | | | | Normal type legalization will widen everything. This requires forcing 0s into the mask register. We can instead choose the form that only reads 2 elements without zeroing the mask. llvm-svn: 319406
* [X86] Make sure we don't remove sign extends of masks with AVX2 masked gathers.Craig Topper2017-11-301-3/+4
| | | | | | We don't use k-registers and instead use the MSB so we need to make sure we sign extend the mask to the msb. llvm-svn: 319405
* AMDGPU: Allow negative MUBUF vaddr for gfx9Matt Arsenault2017-11-302-4/+21
| | | | | | | | GFX9 does not enable bounds checking for the resource descriptors used for private access, so it should be OK to use vaddr with a potentially negative value. llvm-svn: 319393
* [X86] Remove some questionable looking code that seems to be looking through ↵Craig Topper2017-11-291-1/+1
| | | | | | | | | | a VZEXT to create a larger VSEXT. If the input the vzext was signed this would do the wrong thing. Not sure how to test this. llvm-svn: 319382
* First step towards more human-friendly PPC assembler output:Joerg Sonnenberger2017-11-293-32/+74
| | | | | | | | | | | | | | - add -ppc-reg-with-percent-prefix option to use %r3 etc as register names - split off logic for Darwinish verbose conditional codes into a helper function - be explicit about Darwin vs AIX vs GNUish assembler flavors Based on the patch from Alexandre Yukio Yamashita Differential Revision: https://reviews.llvm.org/D39016 llvm-svn: 319381
* [WebAssembly] Update test expectations for gcc torture testsSam Clegg2017-11-291-6/+0
| | | | | | | | | I believe these were recently fixed by: https://reviews.llvm.org/rL319186 Differential Revision: https://reviews.llvm.org/D40619 llvm-svn: 319380
* [WebAssembly] Fix fptoui lowering boundsDan Gohman2017-11-292-14/+47
| | | | | | | To fully avoid trapping on wasm, fptoui needs a second check to ensure that the operand isn't below the supported range. llvm-svn: 319354
* [Hexagon] Remove HexagonISD::PACKHLKrzysztof Parzyszek2017-11-293-6/+1
| | | | llvm-svn: 319352
* [Hexagon] Create helpers extractVector and insertVector in loweringKrzysztof Parzyszek2017-11-292-139/+144
| | | | llvm-svn: 319351
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes (REVERSION)Simon Pilgrim2017-11-292-80/+53
| | | | | | Accidental commit of incomplete patch llvm-svn: 319346
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classesSimon Pilgrim2017-11-292-53/+80
| | | | llvm-svn: 319338
* [X86][AVX512] Tag 3OP (shuffles, double-shifts and GFNI) instructions ↵Simon Pilgrim2017-11-291-76/+91
| | | | | | scheduler classes llvm-svn: 319337
* [ARM][DAG] Revert Disable post-legalization store merge for ARMNirav Dave2017-11-291-0/+3
| | | | | | | | Partially reverting enabling of post-legalization store merge (r319036) for just ARM backend as it is causing incorrect code in some Thumb2 cases. llvm-svn: 319331
* [X86][AVX512] Add itinerary argument to all AVX512_maskable_* wrappers. NFCISimon Pilgrim2017-11-291-44/+49
| | | | | | All default to NoItinerary llvm-svn: 319326
* Reverted r319315 because of unused functions (due to PPR not yet beingSander de Smalen2017-11-293-178/+10
| | | | | | used by any instructions). llvm-svn: 319321
* [X86][AVX512] Tag VPERMILV instruction scheduler classSimon Pilgrim2017-11-292-17/+32
| | | | llvm-svn: 319316
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