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* Use uint16_t to store opcodes in static tables in X86 backend.Craig Topper2012-03-093-24/+30
| | | | llvm-svn: 152391
* Fix undefined behavior in the Mips backend.Ahmed Charles2012-03-092-15/+15
| | | | llvm-svn: 152390
* Fix a regression from r147481.Chad Rosier2012-03-092-1/+8
| | | | | | | | | | | | Original commit message from r147481: DAGCombine for transforming 128->256 casts into a vmovaps, rather then a vxorps + vinsertf128 pair if the original vector came from a load. Fix: Unaligned loads need to generate a vmovups. rdar://10974078 llvm-svn: 152366
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-081-1/+1
| | | | llvm-svn: 152301
* Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:Stepan Dyatkovskiy2012-03-082-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*". ConstCaseIt is just a read-only iterator. CaseIt is read-write iterator; it allows to change case successor and case value. Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters. Main way of iterator usage looks like this: SwitchInst *SI = ... // intialize it somehow for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) { BasicBlock *BB = i.getCaseSuccessor(); ConstantInt *V = i.getCaseValue(); // Do something. } If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method. If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method. There are also related changes in llvm-clients: klee and clang. llvm-svn: 152297
* Invoke setTargetDAGCombine for SELECT.Akira Hatanaka2012-03-081-0/+1
| | | | llvm-svn: 152290
* Swap the operands of a select node if the false (the second) operand is 0.Akira Hatanaka2012-03-081-0/+35
| | | | | | | | | | | | For example, this pattern (select (setcc lhs, rhs, cc), true, 0) is transformed to this one: (select (setcc lhs, rhs, inverse(cc)), 0, true) This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to replace 0 with $zero. llvm-svn: 152285
* Set minimum function alignment to 3 if target is Mips64.Akira Hatanaka2012-03-081-1/+1
| | | | llvm-svn: 152282
* This patch eliminates redundant instructions that produce 0.Akira Hatanaka2012-03-081-1/+50
| | | | | | | | | | | | For example, the first instruction in the code below can be eliminated if the use of $vr0 is replaced with $zero: addiu $vr0, $zero, 0 add $vr2, $vr1, $vr0 add $vr2, $vr1, $zero llvm-svn: 152280
* ARM don't use MCRelaxAll, as it's not safe on ARM.Jim Grosbach2012-03-081-2/+2
| | | | | | | | | The ARM code generator makes aggressive assumptions about the encodings being selected for branches which MCRelaxAll invalidates. rdar://11006355 llvm-svn: 152268
* [fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point Chad Rosier2012-03-071-4/+2
| | | | | | | condition flags to CPSR. This allows us to simplify SelectCmp. Patch by Zonr Chang <zonr.xchg@gmail.com>. llvm-svn: 152243
* ARM pre-v6 assembly parsing for umull/smull.Jim Grosbach2012-03-071-0/+10
| | | | llvm-svn: 152188
* ARM pre-v6 alias for 'nop' to 'mov r0, r0'Jim Grosbach2012-03-071-0/+4
| | | | llvm-svn: 152185
* Tidy up. Remove dead code that slipped into previous commit.Jim Grosbach2012-03-071-6/+0
| | | | llvm-svn: 152184
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-065-39/+58
| | | | | | Register pair, all lanes subscripting. llvm-svn: 152157
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-068-168/+117
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
* Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.Eli Friedman2012-03-061-13/+13
| | | | llvm-svn: 152136
* Tidy up. Kill some dead code.Jim Grosbach2012-03-062-10/+0
| | | | llvm-svn: 152131
* Allow the same types in DPair as in QPR.Jakob Stoklund Olesen2012-03-061-1/+2
| | | | llvm-svn: 152129
* Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.Kevin Enderby2012-03-061-7/+7
| | | | llvm-svn: 152127
* Convert PowerPC to register mask operands.Roman Divacky2012-03-066-122/+52
| | | | llvm-svn: 152122
* Add <imp-def> operands when reloading into physregs.Jakob Stoklund Olesen2012-03-061-0/+4
| | | | | | | | | | When an instruction only writes sub-registers, it is still necessary to add an <imp-def> operand for the super-register. When reloading into a virtual register, rewriting will add the operand, but when loading directly into a virtual register, the <imp-def> operand is still necessary. llvm-svn: 152095
* Split fpscr into two registers: FPSCR and FPSCR_NZCV.Lang Hames2012-03-064-11/+17
| | | | | | | | | The fpscr register contains both flags (set by FP operations/comparisons) and control bits. The control bits (FPSCR) should be reserved, since they're always available and needn't be defined before use. The flag bits (FPSCR_NZCV) should like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165. llvm-svn: 152076
* ARM vpush/vpop assembler mnemonics accept an optional size suffix.Jim Grosbach2012-03-051-0/+8
| | | | | | rdar://10988114 llvm-svn: 152068
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-055-26/+91
| | | | | | Use the new composite physical registers. llvm-svn: 152063
* ARM Remove a bit of dead code.Jim Grosbach2012-03-052-14/+0
| | | | llvm-svn: 152061
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-0511-246/+239
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-0518-27/+37
| | | | | | | Used to allow context sensitive printing of super-register or sub-register references. llvm-svn: 152043
* Address Evan's comments for r151877.Chad Rosier2012-03-051-7/+6
| | | | | | | | | Specifically, remove the magic number when checking to see if the copy has a glue operand and simplify the checking logic. rdar://10930395 llvm-svn: 152041
* updated patch for the ARM fused multiply add/subSebastian Pop2012-03-057-39/+41
| | | | | | | | | | | In this update: - I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2. - I kept setting .fpu=neon-vfpv4 code attribute because that is what the assembler understands. Patch by Ana Pazos <apazos@codeaurora.org> llvm-svn: 152036
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-054-9/+9
| | | | | | static data size. llvm-svn: 152016
* Make aliases for shld and shrd match gas. PR12173.Eli Friedman2012-03-051-14/+14
| | | | llvm-svn: 152014
* Use <def,undef> operands when spilling NEON bundles.Jakob Stoklund Olesen2012-03-041-14/+12
| | | | | | | | | | | MachineOperands that define part of a virtual register must have an <undef> flag if they are not intended as read-modify-write operands. The old trick of adding an <imp-def> operand doesn't work any longer. Fixes PR12177. llvm-svn: 152008
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-045-11/+11
| | | | llvm-svn: 152001
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper2012-03-043-15/+15
| | | | | | static data size. llvm-svn: 151998
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-0424-45/+45
| | | | | | size of static data. llvm-svn: 151996
* Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper2012-03-042-4/+4
| | | | | | Shaves 150k off the size of X86DisassemblerDecoder.o llvm-svn: 151995
* Prevent obscure and incorrect tail-call optimization.Chad Rosier2012-03-021-0/+5
| | | | | | | | | | | | In this instance we are generating the tail-call during legalizeDAG. The 2nd floor call can't be a tail call because it clobbers %xmm1, which is defined by the first floor call. The first floor call can't be a tail-call because it's not in the tail position. The only reasonable way I could think to fix this in a target-independent manner was to check for glue logic on the copy reg. rdar://10930395 llvm-svn: 151877
* Neuter the optimization I implemented with r107852 and r108258 which turn someEvan Cheng2012-03-011-8/+12
| | | | | | | | | | | | floating point equality comparisons into integer ones with -ffast-math. The issue is the optimization causes +0.0 != -0.0. Now the optimization is only done when one side is known to be 0.0. The other side's sign bit is masked off for the comparison. rdar://10964603 llvm-svn: 151861
* Handle regmasks in Thumb1RegisterInfo::saveScavengerRegister().Jakob Stoklund Olesen2012-03-011-0/+5
| | | | | | | | | | | | | | This function could have r12 live across a function call when compiling thumb1 code. The test case for this is not included because it is very long. It must provoke emergency spilling near a function call. The behavior is provoked by MultiSource/Applications/JM/lencod, and it triggers an assertion in the scavenger. <rdar://problem/10963642> llvm-svn: 151855
* ARM use the right opcode for FP<->Integer move in fast-isel.Jim Grosbach2012-03-011-2/+2
| | | | | | rdar://10965031 llvm-svn: 151850
* Minimal changes for LLVM to compile under VS11.Michael J. Spencer2012-03-011-0/+4
| | | | llvm-svn: 151849
* Changes for migrating to using register mask operands.Akira Hatanaka2012-03-016-48/+45
| | | | llvm-svn: 151847
* Change ARMInstPrinter::printPredicateOperand() so it will not abort if itKevin Enderby2012-03-011-1/+4
| | | | | | runs into the undefined 15 condition code value. llvm-svn: 151844
* Fix bugs which were introduced when support for base+index floating point loadsAkira Hatanaka2012-03-014-10/+35
| | | | | | | | | | | and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
* Make TargetRegisterClasses non-virtual by making the only virtual function a ↵Benjamin Kramer2012-03-011-2/+0
| | | | | | | | | | | function pointer. This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static initializer and a ton of cruft from the generated code. Shrinks ARMBaseRegisterInfo.o by ~100k. llvm-svn: 151806
* Emit the "is an intrinsic overloaded" table as a bitfield.Benjamin Kramer2012-03-011-7/+4
| | | | llvm-svn: 151792
* Pass endian information to constructors. Define separate functions to createAkira Hatanaka2012-03-015-57/+55
| | | | | | | | objects for big endian and little endian targets. Patch by Jack Carter. llvm-svn: 151788
* Added annotations for x86 pc relative loads to llvm's 'C' disassembler.Kevin Enderby2012-02-291-0/+24
| | | | | | | So with darwin's otool(1) an x86_64 hello world .o file will print: leaq L_.str(%rip), %rax ## literal pool for: Hello world llvm-svn: 151769
* Intel Atom instruction itineraries for mov sign extension and mov zero ↵Andrew Trick2012-02-293-32/+68
| | | | | | | | extension. Patch by Tyler Nowicki! llvm-svn: 151743
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