summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* [Cygwin] Use -femulated-tls by default since r257718 introduced the new pass.NAKAMURA Takumi2016-01-161-5/+1
| | | | | | FIXME: Add more targets to use emutls into clang/test/Driver/emulated-tls.cpp. FIXME: Add cygwin tests into llvm/test/CodeGen/X86. Working in progress. llvm-svn: 257984
* [WebAssembly] Add some more README.txt entries.Dan Gohman2016-01-161-0/+10
| | | | llvm-svn: 257969
* [X86]: Make param names in header and body match for isCalleePop.Kevin B. Smith2016-01-161-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D16246 llvm-svn: 257965
* [WebAssembly] Don't create a needless .note.GNU-stack sectionDan Gohman2016-01-151-0/+3
| | | | | | | | | | WebAssembly's stack will never be executable by default, so it isn't necessary to declare .note.GNU-stack sections to request a non-executable stack. Differential Revision: http://reviews.llvm.org/D15969 llvm-svn: 257962
* [NVPTX] Do not emit .hidden or .protected directives as they are not allowed ↵Artem Belevich2016-01-151-0/+3
| | | | | | by PTX. llvm-svn: 257961
* CXX_FAST_TLS calling convention: fix issue on ARM.Manman Ren2016-01-151-4/+5
| | | | | | | | | | When we have a single basic block, the explicit copy-back instructions should be inserted right before the terminator. Before this fix, they were wrongly placed at the beginning of the basic block. PR26136 llvm-svn: 257930
* CXX_FAST_TLS calling convention: fix issue on AArch64.Manman Ren2016-01-151-4/+5
| | | | | | | | | | | | When we have a single basic block, the explicit copy-back instructions should be inserted right before the terminator. Before this fix, they were wrongly placed at the beginning of the basic block. I will commit fixes to other platforms as well. PR26136 llvm-svn: 257929
* CXX_FAST_TLS calling convention: fix issue on X86-64.Manman Ren2016-01-151-4/+5
| | | | | | | | | | | | When we have a single basic block, the explicit copy-back instructions should be inserted right before the terminator. Before this fix, they were wrongly placed at the beginning of the basic block. I will commit fixes to other platforms as well. PR26136 llvm-svn: 257925
* Codegen: [PPC] Silence false-positive initialization warning. NFCKyle Butt2016-01-151-2/+2
| | | | | | | | | | Some compilers don't do exhaustive switch checking. For those compilers, add an initialization to prevent un-initialized variable warnings from firing. For compilers with exhaustive switch checking, we still get a guarantee that the switch is exhaustive, and hence the initializations are redundant, and a non-functional change. llvm-svn: 257923
* Revert "[ARM] Add ARMv8-M security extension instructions to ARMv8-M ↵Reid Kleckner2016-01-158-94/+1
| | | | | | | | | | Baseline/Mainline" This reverts commit r257883. Somehow this didn't make it into r257916. llvm-svn: 257919
* # This is a combination of 2 commits.Reid Kleckner2016-01-155-115/+7
| | | | | | | | | | | | | | | | # The first commit's message is: Revert "[ARM] Add DSP build attribute and extension targeting" This reverts commit b11cc50c0b4a7c8cdb628abc50b7dc226ff583dc. # This is the 2nd commit message: Revert "[ARM] Add new system registers to ARMv8-M Baseline/Mainline" This reverts commit 837d08454e3e5beb8581951ac26b22fa07df3cd5. llvm-svn: 257916
* [Hexagon] Generate CONST64 when optimizing for size in copy-to-combineKrzysztof Parzyszek2016-01-151-11/+64
| | | | llvm-svn: 257891
* [Hexagon] Handle DBG_VALUE instructions in copy-to-combineKrzysztof Parzyszek2016-01-151-7/+49
| | | | llvm-svn: 257890
* [ARM] Add DSP build attribute and extension targetingBradley Smith2016-01-151-0/+3
| | | | llvm-svn: 257885
* [ARM] Add new system registers to ARMv8-M Baseline/MainlineBradley Smith2016-01-154-7/+112
| | | | llvm-svn: 257884
* [ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-158-1/+94
| | | | llvm-svn: 257883
* [ARM] Add ARMv8-A semaphore/atomic instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-155-14/+25
| | | | llvm-svn: 257882
* [ARM] Add B.W and CBZ instructions to ARMv8-M BaselineBradley Smith2016-01-155-11/+23
| | | | llvm-svn: 257881
* [ARM] Add SDIV/UDIV instructions to ARMv8-M BaselineBradley Smith2016-01-152-4/+5
| | | | llvm-svn: 257880
* [ARM] Add MOVW/MOVT instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-153-12/+15
| | | | llvm-svn: 257879
* [ARM] Add ARMv8-M Baseline/Mainline LLVM targetingBradley Smith2016-01-156-5/+59
| | | | llvm-svn: 257878
* [ARM] Split out ARMv8-A semaphores and atomics and ARMv7 clrex as separate ↵Bradley Smith2016-01-156-22/+53
| | | | | | features llvm-svn: 257877
* [SystemZ] Fix bad instruction nameJonas Paulsson2016-01-151-1/+1
| | | | | | | | SLGBR -> SLBGR Reviewed by Ulrich Weigand llvm-svn: 257874
* Delete MCRelocationInfo::createExprForRelocation.Pete Cooper2016-01-155-272/+0
| | | | | | | | | | | This method has no callers. Also remove X86ELFRelocationInfo.cpp and X86MachORelocationInfo.cpp which only existed to provide an implementation of that method. Ok'd by Rafael and Jim. llvm-svn: 257859
* Fix AArch64ConditionOptimizerWeiming Zhao2016-01-151-0/+8
| | | | | | | | | | | | | | Summary: This pass may modify the Cmp operands. However, the flag reg may be used by both the branch and CSEL. Modifying CMP will have side effect on CSEL. Reviewers: t.p.northover Subscribers: llvm-commits, aemerson, rengolin Differential Revision: http://reviews.llvm.org/D16147 llvm-svn: 257844
* [Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfwordKrzysztof Parzyszek2016-01-141-3/+2
| | | | llvm-svn: 257815
* [Hexagon] Handle HVX registers in bit simplificationKrzysztof Parzyszek2016-01-141-0/+6
| | | | llvm-svn: 257811
* Update to use new name alignTo().Rui Ueyama2016-01-1418-50/+48
| | | | llvm-svn: 257804
* Handle offsets larger than 32 bits.Rafael Espindola2016-01-141-2/+4
| | | | | | | David Majnemer noticed that it was not obvious what the behavior would be if B.Offset - A.Offset could not fit in an int. llvm-svn: 257803
* Assert that a cmp function defines a total order.Rafael Espindola2016-01-141-3/+2
| | | | | | Thanks to David Blaikie for noticing it. llvm-svn: 257796
* [Hexagon] Expand pseudo instruction Insert4Krzysztof Parzyszek2016-01-141-0/+30
| | | | llvm-svn: 257771
* [Hexagon] Handle branches with non-mbb operandsKrzysztof Parzyszek2016-01-142-0/+7
| | | | llvm-svn: 257768
* [ARM] Use the efficient version of BitVector::set and a static_assert.Benjamin Kramer2016-01-141-3/+2
| | | | | | No functional change intended. llvm-svn: 257766
* AVX512: VMOVDQA32/64 (load) intrinsic implementation.Igor Breger2016-01-141-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D16142 llvm-svn: 257749
* [AArch64] Don't assume extractelt constant index when matching shuffle.Ahmed Bougacha2016-01-141-2/+3
| | | | llvm-svn: 257735
* WebAssembly: mark a few new failuresJF Bastien2016-01-141-0/+8
| | | | | | | | | | | | A recent change introduced this assertion failure in some corner cases. Repro: mkdir /s/wasm/torture-out ; time /s/wasm/waterfall/src/compile_torture_tests.py --c /s/llvm/out/bin/clang --cxx /s/llvm/out/bin/clang++ --testsuite /s/gcc/gcc/testsuite --fails /s/llvm/llvm/lib/Target/WebAssembly/known_gcc_test_failures.txt --out /s/wasm/torture-out Or look on the wasm integration bot: https://build.chromium.org/p/client.wasm.llvm/console llvm-svn: 257733
* [X86] Don't alter HasOpaqueSPAdjustment after we've relied on itDavid Majnemer2016-01-142-7/+8
| | | | | | | | | | | | | | We rely on HasOpaqueSPAdjustment not changing after we've calculated things based on it. Things like whether or not we can use 'rep;movs' to copy bytes around, that sort of thing. If it changes, invariants in the backend will quietly break. This situation arose when we had a call to memcpy *and* a COPY of the FLAGS register where we would attempt to reference local variables using %esi, a register that was clobbered by the 'rep;movs'. This fixes PR26124. llvm-svn: 257730
* WebAssembly: fix build break introduced by ELFObjectWriter churnJF Bastien2016-01-132-4/+5
| | | | llvm-svn: 257709
* Convert a few assert failures into proper errors.Rafael Espindola2016-01-1310-38/+51
| | | | | | Fixes PR25944. llvm-svn: 257697
* [Hexagon] Fix the options controlling jump table generationKrzysztof Parzyszek2016-01-131-2/+2
| | | | llvm-svn: 257679
* AMDGPU/SI: Update ISA version for FIJIChangpeng Fang2016-01-134-2/+7
| | | | llvm-svn: 257666
* [WebAssembly] Add an assertion to catch unexpected MCFixupKindInfo flags.Dan Gohman2016-01-131-0/+2
| | | | llvm-svn: 257657
* [WebAssembly] MCFixupKindInfo's TargetSize is in bits rather than bytes.Dan Gohman2016-01-131-2/+2
| | | | llvm-svn: 257655
* Fix struct/class mismatch for MachineSchedContextHans Wennborg2016-01-131-1/+1
| | | | llvm-svn: 257648
* AMDGPU/SI: Fix a GPU hang with POS_W_FLOAT enabledMarek Olsak2016-01-131-1/+8
| | | | | | | | | | Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16037 llvm-svn: 257625
* AMDGPU/SI: Remove ending s_endpgm from non-void functionsMarek Olsak2016-01-131-0/+8
| | | | | | | | | | Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16035 llvm-svn: 257623
* AMDGPU/SI: Add s_waitcnt at the end of non-void functionsMarek Olsak2016-01-134-1/+19
| | | | | | | | | | | | | | Summary: v2: Make ReturnsVoid private, so that I can another 8 lines of code and look more productive. Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16034 llvm-svn: 257622
* AMDGPU/SI: Add support for non-void functionsMarek Olsak2016-01-136-1/+136
| | | | | | | | | | | | | | | | | | | Summary: Return values can be stored in SGPRs (i32) and VGPRs (f32). This will be used by functions which expect some bytecode or other binary to be appended at the end. It allows defining in which registers the return values will be stored. v2: don't do this for compute shaders Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16033 llvm-svn: 257621
* [WebAssemly] Invalidate liveness in CFG stackifierDerek Schuff2016-01-131-0/+3
| | | | | | | WebAssemblyCFGStackify does not track liveness for EXPR_STACK, causing verifier failure if liveness has not already been invalidated. llvm-svn: 257620
* AMDGPU/SI: Add SI Machine SchedulerNicolai Haehnle2016-01-139-3/+2503
| | | | | | | | | | | | | | | | Summary: It is off by default, but can be used with --misched=si Patch by: Axel Davy Reviewers: arsenm, tstellarAMD, nhaehnle Subscribers: nhaehnle, solenskiner, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D11885 llvm-svn: 257609
OpenPOWER on IntegriCloud