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* Convert assert(0) to llvm_unreachable in X86 Target directory.Craig Topper2012-02-058-22/+20
| | | | llvm-svn: 149809
* Convert some assert(0) in default of switch statements to llvm_unreachable.Craig Topper2012-02-051-10/+7
| | | | llvm-svn: 149808
* Add target specific node for PMULUDQ. Change patterns to use it and custom ↵Craig Topper2012-02-054-69/+69
| | | | | | lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. llvm-svn: 149807
* reapply the patches reverted in r149470 that reenable ConstantDataArray,Chris Lattner2012-02-052-96/+25
| | | | | | | | | but with a critical fix to the SelectionDAG code that optimizes copies from strings into immediate stores: the previous code was stopping reading string data at the first nul. Address this by adding a new argument to llvm::getConstantStringInfo, preserving the behavior before the patch. llvm-svn: 149800
* Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased ↵Craig Topper2012-02-051-125/+0
| | | | | | to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file. llvm-svn: 149795
* TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick2012-02-0422-87/+62
| | | | | | | | | | Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. llvm-svn: 149754
* [fast-isel] Add support for URem.Chad Rosier2012-02-031-8/+10
| | | | llvm-svn: 149716
* [fast-isel] Rename isZExt to isSigned. No functional change intended.Chad Rosier2012-02-031-13/+14
| | | | llvm-svn: 149714
* [fast-isel] Add support for UDIV.Chad Rosier2012-02-031-8/+10
| | | | llvm-svn: 149712
* [fast-isel] Add support for FPToUI. Also add test cases for FPToSI.Chad Rosier2012-02-031-6/+8
| | | | llvm-svn: 149706
* [fast-isel] Add support for selecting UIToFP.Chad Rosier2012-02-031-6/+8
| | | | llvm-svn: 149704
* Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate ↵Craig Topper2012-02-031-30/+1
| | | | | | performs the same calculation. llvm-svn: 149683
* Remove unnecessary qualification on 256-bit vector handling in ↵Craig Topper2012-02-031-2/+2
| | | | | | LowerBUILD_VECTOR. Condition was already guaranteed by earlier code. llvm-svn: 149680
* Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2012-02-0322-154/+401
| | | | | | | | | | | Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. llvm-svn: 149672
* whitespaceAndrew Trick2012-02-034-15/+15
| | | | llvm-svn: 149671
* Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which isAkira Hatanaka2012-02-034-3/+16
| | | | | | | | needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
* Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.Lang Hames2012-02-031-22/+33
| | | | llvm-svn: 149655
* Require non-NULL register masks.Jakob Stoklund Olesen2012-02-021-2/+2
| | | | | | | It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. llvm-svn: 149646
* Add pseudo-registers for pairs, triples, and quads of D registers.Jakob Stoklund Olesen2012-02-021-15/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | NEON loads and stores accept single and double spaced pairs, triples, and quads of D registers. This patch adds new register classes to accurately model those constraints: Dn, Dn+1 Dn, Dn+2 ---------------------- DPair DPairSpc DTriple DTripleSpc DQuad DQuadSpc Also extend the existing QQ and QQQQ register classes to contains all Q pairs and quads instead of just the aligned ones. These new register classes will make it possible to accurately model constraints on NEON loads and stores, and we can get rid of all the NEON pseudo-instructions. The late scheduler will be able to accurately model instruction dependencies from the explicit operands. This more than doubles the number of ARM registers, but the backend passes are quite good at handling this. The llc -O0 compile time only regresses by 1.5%. Future work on register mask operands will recover this regression. llvm-svn: 149640
* Minor change in signature of the getZeroVector() Elena Demikhovsky2012-02-021-30/+21
| | | | llvm-svn: 149601
* Optimization for SIGN_EXTEND operation on AVX.Elena Demikhovsky2012-02-024-0/+67
| | | | | | | Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32 extensions. llvm-svn: 149600
* Unbreak the MSVC build.Francois Pichet2012-02-021-1/+1
| | | | llvm-svn: 149599
* Set EFLAGS correctly in EmitLoweredSelect on X86.Lang Hames2012-02-021-2/+29
| | | | llvm-svn: 149597
* Set the correct stack pointer register.Akira Hatanaka2012-02-021-1/+1
| | | | llvm-svn: 149585
* Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer andAkira Hatanaka2012-02-021-2/+4
| | | | | | | selector registers. llvm-svn: 149584
* Add DWARF numbers of 64-bit registers.Akira Hatanaka2012-02-021-64/+64
| | | | llvm-svn: 149583
* Fix the cmake buildRafael Espindola2012-02-011-0/+1
| | | | llvm-svn: 149561
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-0115-514/+1016
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
* Move ARM subreg index compositions to the SubRegIndex itself.Jakob Stoklund Olesen2012-02-011-28/+22
| | | | llvm-svn: 149557
* Avoid creating an extract element to an illegal type after LegalizeTypes has ↵Mon P Wang2012-02-011-2/+10
| | | | | | run. llvm-svn: 149548
* VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick2012-02-015-0/+42
| | | | | | | | | | automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! llvm-svn: 149547
* Tidy up.Chad Rosier2012-02-011-1/+1
| | | | llvm-svn: 149521
* Passing AVX 256-bit structures in Win64 was wrong.Elena Demikhovsky2012-02-011-0/+4
| | | | | | Fixed Win64 calling conventions. llvm-svn: 149494
* Shortened code in shuffle masksElena Demikhovsky2012-02-011-33/+11
| | | | llvm-svn: 149493
* Optimization for "truncate" operation on AVX.Elena Demikhovsky2012-02-012-0/+101
| | | | | | Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles. llvm-svn: 149485
* SwitchInst refactoring.Stepan Dyatkovskiy2012-02-012-4/+4
| | | | | | | | | | | | | | | | | The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want. What was done: 1. Changed semantics of index inside the getCaseValue method: getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous. 2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned. 3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment. 4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst. 4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor. 4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor. Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang. llvm-svn: 149481
* Don't create VBROADCAST nodes if any nodes use the chain result from the ↵Craig Topper2012-02-011-0/+4
| | | | | | load. Fixes PR11900. llvm-svn: 149478
* Revert Chris' commits up to r149348 that started causing VMCoreTests unit ↵Argyrios Kyrtzidis2012-02-012-25/+96
| | | | | | | | | | | | | | | | | | | test to fail. These are: r149348 r149351 r149352 r149354 r149356 r149357 r149361 r149362 r149364 r149365 llvm-svn: 149470
* Tidy up. One more return type mismatch fix.Jim Grosbach2012-01-311-1/+1
| | | | llvm-svn: 149452
* Refactor loop for better readability.Jim Grosbach2012-01-311-3/+2
| | | | | | Excellent suggestion from Ben Kramer. llvm-svn: 149417
* Add explanatory comment.Jim Grosbach2012-01-311-0/+1
| | | | llvm-svn: 149416
* Add assembler dialect attribute in asm parser which lets target specific asm ↵Devang Patel2012-01-311-4/+3
| | | | | | parser change dialect on the fly. llvm-svn: 149396
* Remove pcmpgt/pcmpeq intrinsics as clang is not using them.Craig Topper2012-01-311-20/+0
| | | | llvm-svn: 149367
* with recent changes, ConstantArray is never a "string". Remove the associatedChris Lattner2012-01-312-96/+25
| | | | | | methods and constant fold the clients to false. llvm-svn: 149362
* use the right accessor for ConstantDataArray.Chris Lattner2012-01-311-1/+1
| | | | llvm-svn: 149342
* PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina.Evan Cheng2012-01-302-2/+4
| | | | llvm-svn: 149294
* Intel syntax. Adjust special code, used to recognize cmp<comparison ↵Devang Patel2012-01-301-2/+4
| | | | | | code>{ss,sd,ps,pd}, for intel syntax. llvm-svn: 149291
* Intel syntax. Support .intel_syntax directive.Devang Patel2012-01-301-10/+24
| | | | llvm-svn: 149270
* Fix refacto.Benjamin Kramer2012-01-301-2/+2
| | | | llvm-svn: 149269
* Eliminate narrowing conversion in initializer list, to make C++11 happyDouglas Gregor2012-01-301-2/+2
| | | | llvm-svn: 149254
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