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* AArch64/ARM64: accept and print floating-point immediate 0 as "#0.0"Tim Northover2014-04-302-19/+41
| | | | | | | | | | It's been decided that in the future, the floating-point immediate in instructions like "fcmeq v0.2s, v1.2s, #0.0" will be canonically "0.0", which has been implemented on AArch64 already but not ARM64. This fixes that issue. llvm-svn: 207666
* [mips] Add instruction alias (dsll and dsrl).Matheus Almeida2014-04-301-0/+4
| | | | | | | | | | | | | | Summary: The pattern dsll/dsrl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of dsllv/dsrlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3486 llvm-svn: 207664
* R600/SI: Use VALU instructions for copying i1 valuesTom Stellard2014-04-309-9/+149
| | | | | | | | | We can't use SALU instructions for this since they ignore the EXEC mask and are always executed. This fixes several OpenCV tests. llvm-svn: 207661
* R600/SI: Teach moveToVALU how to handle some SMRD instructionsTom Stellard2014-04-302-1/+49
| | | | llvm-svn: 207660
* [ARM64][fast-isel] Fast-isel doesn't know how to handle f128.Chad Rosier2014-04-301-1/+14
| | | | llvm-svn: 207659
* [mips] Add instruction alias (sll and srl).Matheus Almeida2014-04-301-0/+4
| | | | | | | | | | | | | | Summary: The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of sllv/srlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3483 llvm-svn: 207657
* [mips] Fix MipsLongBranch pass to work when the offset from the branch to theSasa Stankovic2014-04-308-33/+169
| | | | | | | | | | | | | | target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. llvm-svn: 207656
* R600: Remove unused function AMDGPUSubtarget::getDefaultSize()Tom Stellard2014-04-302-13/+0
| | | | llvm-svn: 207654
* [asan] Disable asm instrumentation on unsupported platforms.Evgeniy Stepanov2014-04-301-3/+6
| | | | | | | | | Only emit calls to compiler-rt asm routines on platforms where they are present (currently limited to linux i386/x86_64). Patch by Yuri Gorshenin. llvm-svn: 207651
* ARM64: print lsr instead of lsrv for variable shifts (etc)Tim Northover2014-04-301-13/+13
| | | | | | | The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
* ARM64: use 32-bit operations for uxtb & uxthTim Northover2014-04-301-3/+19
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s llvm-svn: 207648
* AArch64/ARM64: allow smaller granule relocations on MOVZ/MOVNTim Northover2014-04-301-6/+6
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s llvm-svn: 207647
* AArch64/ARM64: copy support for bCC instead of b.CC across.Tim Northover2014-04-301-0/+21
| | | | llvm-svn: 207646
* AArch64/ARM64: expunge CPSR from the sourcesTim Northover2014-04-3012-123/+125
| | | | | | | | | | | | AArch64 does not have a CPSR register in the same way that AArch32 does. Most of its compiler-relevant roles have been taken over by the more specific NZCV register (representing just the flags set by normal instructions). Its system control functions still remain, but are now under the pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR instructions described in the reference manual. llvm-svn: 207645
* AArch64/ARM64: use HS instead of CS & LO instead of CC.Tim Northover2014-04-304-20/+20
| | | | | | | | | On instructions using the NZCV register, a couple of conditions have dual representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and unsigned-lower/carry-clear). The first of these is more descriptive in most circumstances, so we should print it. llvm-svn: 207644
* [mips][msa] Fix vector insertions where the index is variableDaniel Sanders2014-04-303-0/+172
| | | | | | | | | | | | | | | | | | | | | Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
* ARM64: accept ELF-relocated load/store insts without a #.Tim Northover2014-04-301-0/+1
| | | | | | | E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax too. llvm-svn: 207639
* ARM64: remove duplication by templating InstPrinter methodsTim Northover2014-04-304-215/+65
| | | | | | No functional change, so no tests. llvm-svn: 207638
* [mips] Add support for .cpload.Matheus Almeida2014-04-303-0/+100
| | | | | | | | | | | | | | | | | | | | Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 llvm-svn: 207637
* ARM64: use hex immediates for movz/movk instructionsTim Northover2014-04-301-0/+1
| | | | | | | | Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to piece together an immediate in 16-bit chunks, hex is probably the most appropriate format. llvm-svn: 207635
* ARM64: hexify printing various immediate operandsTim Northover2014-04-303-0/+10
| | | | | | | | | | This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. llvm-svn: 207634
* ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover2014-04-301-3/+5
| | | | | | | | | | Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. llvm-svn: 207633
* [ARM64] Simplify if condition.James Molloy2014-04-301-6/+2
| | | | | | | v2f32 and v4f32 were missed out of these conditions, so this is also a bugfix. llvm-svn: 207628
* [ARM64] Fix stupid copy-pasto in ARM64MCAsmInfo.cpp - aarch64_be -> arm64_beJames Molloy2014-04-301-1/+1
| | | | llvm-svn: 207627
* ARM64: make sure FastISel uses a GPR64 source in 64-bit extensions.Tim Northover2014-04-301-0/+9
| | | | llvm-svn: 207620
* Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I ↵Craig Topper2014-04-308-30/+25
| | | | | | introduced most of these recently. llvm-svn: 207616
* ARM: support stack probe emission for Windows on ARMSaleem Abdulrasool2014-04-301-4/+59
| | | | | | | | | | | | | | | | | This introduces the stack lowering emission of the stack probe function for Windows on ARM. The stack on Windows on ARM is a dynamically paged stack where any page allocation which crosses a page boundary of the following guard page will cause a page fault. This page fault must be handled by the kernel to ensure that the page is faulted in. If this does not occur and a write access any memory beyond that, the page fault will go unserviced, resulting in an abnormal program termination. The watermark for the stack probe appears to be at 4080 bytes (for accommodating the stack guard canaries and stack alignment) when SSP is enabled. Otherwise, the stack probe is emitted on the page size boundary of 4096 bytes. llvm-svn: 207615
* ARM: print COFF function header for Windows on ARMSaleem Abdulrasool2014-04-301-1/+23
| | | | | | | | | Emit the COFF header when printing out the function. This is important as the header contains two important pieces of information: the storage class for the symbol and the symbol type information. This bit of information is required for the linker to correctly identify the type of symbol that it is dealing with. llvm-svn: 207613
* De-virtualize or remove some methods that have no overrides nor override ↵Craig Topper2014-04-307-27/+7
| | | | | | anything. In some cases remove all together if there are no callers either. llvm-svn: 207610
* ARM: move llvm_unreachable useSaleem Abdulrasool2014-04-301-1/+1
| | | | | | | | When building with -Werror=covered-switch-default (as on the buildbots), the build would fail since all cases are covered by the switch. Move the llvm_unreachable to the end of the function as an annotation. llvm-svn: 207609
* ARM: partially handle 32-bit relocations for WoASaleem Abdulrasool2014-04-301-0/+45
| | | | | | | | | | | | | | | IMAGE_REL_ARM_MOV32T relocations require that the movw/movt pair-wise relocation is not split up and reordered. When expanding the mov32imm pseudo-instruction, create a bundle if the machine operand is referencing an address. This helps ensure that the relocatable address load is not reordered by subsequent passes. Unfortunately, this only partially handles the case as the Constant Island Pass occurs after the instructions are unbundled and does not properly handle bundles. That is a more fundamental issue with the pass itself and beyond the scope of this change. llvm-svn: 207608
* Implement X86 code generation for musttailReid Kleckner2014-04-291-45/+50
| | | | | | | | | | | | | | | | | | Currently, musttail codegen is relying on sibcall optimization, and reporting a fatal error if fails. Sibcall optimization fails when stack arguments need to be modified, which is insufficient for musttail. The logic for moving arguments in memory safely is already implemented for GuaranteedTailCallOpt. This change merely arranges for musttail calls to use it. No functional change for GuaranteedTailCallOpt. Reviewers: espindola Differential Revision: http://reviews.llvm.org/D3493 llvm-svn: 207598
* raw_ostream: Forward declare OpenFlags and include FileSystem.h only where ↵Benjamin Kramer2014-04-291-0/+1
| | | | | | necessary. llvm-svn: 207593
* R600: Remove duplicate setting of SELECT expansion.Tom Stellard2014-04-291-2/+0
| | | | | | | | | | It's already set in AMDGPUISelLowering for all GPUs Patch By: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207592
* R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errorsTom Stellard2014-04-292-15/+63
| | | | | | | | | | | | | | | | SI_IF and SI_ELSE are terminators which also produce a value. For these instructions ISel always inserts a COPY to move their value to another basic block. This COPY ends up between SI_(IF|ELSE) and the S_BRANCH* instruction at the end of the block. This breaks MachineBasicBlock::getFirstTerminator() and also the machine verifier which assumes that terminators are grouped together at the end of blocks. To solve this we coalesce the copy away right after ISel to make sure there are no instructions in between terminators at the end of blocks. llvm-svn: 207591
* R600/SI: Only select SALU instructions in the entry or exit blockTom Stellard2014-04-292-27/+117
| | | | | | | | SALU instructions ignore control flow, so it is not always safe to use them within branches. This is a partial solution to this problem until we can come up with something better. llvm-svn: 207590
* R600: optimize the UDIVREM 64 algorithmTom Stellard2014-04-291-22/+44
| | | | | | | | | | | | | | | | This is a squash of several optimization commits: - calculate DIV_Lo and DIV_Hi separately - use BFE_U32 if we are operating on 32bit values - use precomputed constants instead of shifting in UDVIREM - skip the first 32 iterations of udivrem v2: Check whether BFE is supported before using it Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207589
* R600: Implement iterative algorithm for udivremTom Stellard2014-04-291-0/+50
| | | | | | | | | | Initial implementation, rather slow Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207588
* R600: Change UDIV/UREM to UDIVREM when legalizing typesTom Stellard2014-04-293-1/+28
| | | | | | | | | | | | | | | | | | When legalizing ops, with UDIV/UREM set to expand, they automatically expand to UDIVREM (if legal or custom). We need to do this manually for legalize types. v2: SI should be set to Expand because the type is legal, and it is automatically lowered to UDIVREM if UDIVREM is Legal/Custom R600 should set to UDIV/UREM to Custom because it needs to lower them during type legalization Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207587
* R600: remove unused variableTom Stellard2014-04-291-2/+0
| | | | | | | | Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207586
* Add Simple return instruction to Mips fast-iselReed Kotler2014-04-291-2/+58
| | | | | | | | | | Reviewers: dsanders Reviewed by: dsanders Differential Revision: http://reviews.llvm.org/D3430 llvm-svn: 207565
* [mips] Remove two more redundant 'let Predicates = [HasStdEnc]' statements ↵Daniel Sanders2014-04-291-2/+2
| | | | | | | | | | | | | | that were missed Summary: The InstSE class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3548 llvm-svn: 207558
* [mips] Remove more redundant 'let Predicates = [HasStdEnc]' statementsDaniel Sanders2014-04-291-10/+6
| | | | | | | | | | | | Summary: The InstSE class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3547 llvm-svn: 207551
* [mips] Remove redundant 'let Predicates = [HasStdEnc]' statementsDaniel Sanders2014-04-293-21/+12
| | | | | | | | | | | | Summary: The MipsPat class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3546 llvm-svn: 207548
* Parse and create GOT_PREL relocations.Joerg Sonnenberger2014-04-291-0/+6
| | | | llvm-svn: 207526
* [mips][msa] Fix element extraction where the index is variable.Daniel Sanders2014-04-291-0/+52
| | | | | | | | | | | | | | Summary: This isn't supported directly so we splat the vector element and extract the most convenient copy. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3530 llvm-svn: 207524
* Centralize the handling of the thumb bit.Rafael Espindola2014-04-292-7/+3
| | | | | | | | | | | | | This patch centralizes the handling of the thumb bit around MCStreamer::isThumbFunc and makes isThumbFunc handle aliases. This fixes a corner case, but the main advantage is having just one way to check if a MCSymbol is thumb or not. This should still be refactored to be ARM only, but at least now it is just one predicate that has to be refactored instead of 3 (isThumbFunc, ELF_Other_ThumbFunc, and SF_ThumbFunc). llvm-svn: 207522
* X86: emit hidden stubs into a proper non_lazy_symbol_pointer section.Tim Northover2014-04-291-31/+35
| | | | | | rdar://problem/16660411 llvm-svn: 207518
* ARM: emit hidden stubs into a proper non_lazy_symbol_pointer section.Tim Northover2014-04-291-31/+30
| | | | | | rdar://problem/16660411 llvm-svn: 207517
* AArch64: Mark vector long multiplication as expand.Benjamin Kramer2014-04-291-0/+5
| | | | | | | There are no patterns for this. This was already fixed for ARM64 but I forgot to apply it to AArch64 too. llvm-svn: 207515
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