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* Pass Divergence Analysis data to Selection DAG to drive divergenceAlexander Timofeev2018-03-058-57/+162
| | | | | | | | dependent instruction selection. Differential revision: https://reviews.llvm.org/D35267 llvm-svn: 326703
* [Power9] Add more missing instructions to the Power 9 schedulerStefan Pintilie2018-03-052-38/+150
| | | | | | | Adding more instructions using InstRW so that we can move away from ItinRW and ultimately have a complete Power 9 scheduler. llvm-svn: 326701
* [ARM][Asm] VMOVSRR and VMOVRRS need sequential S registersOliver Stannard2018-03-051-0/+18
| | | | | | | | | | These instructions require that the two S registers are adjacent (but not the R registers), because only the first register is included in the encoding, but we were not checking this in the assembler. Differential revision: https://reviews.llvm.org/D44084 llvm-svn: 326696
* Fix location of comment in EmitPopInstThomas Preud'homme2018-03-051-1/+1
| | | | | | | Comment about folding return in LDM was not moved along with the corresponding code in r242714. This commit fixes that. llvm-svn: 326690
* [X86] Replace usages of X86Subtarget::hasFp256 with hasAVX. Remove hasFP256.Craig Topper2018-03-053-11/+10
| | | | | | | | Almost none of these usages were FP specific. And we had no clear guideliness on when to use hasAVX vs hasFP256. I might also remove hasInt256 too since its an alias for hasAVX2. llvm-svn: 326682
* [X86] Add a DAG combine to turn stores of vXi1 constants into scalar stores.Craig Topper2018-03-042-4/+47
| | | | llvm-svn: 326679
* [X86][MMX] Remove completed _mm_cvtsi32_si64 todoSimon Pilgrim2018-03-041-29/+0
| | | | | | | | | | rL322525 - mmx zero constant support rL322553 - mmx i32 zero extended value rL326497 - mmx i64 general constant handling Not all constants are folded, we generate some on the GPRs (similar to SSE build vector) where appropriate llvm-svn: 326673
* [X86] Fix unused variable in release builds.Craig Topper2018-03-041-4/+5
| | | | llvm-svn: 326672
* [X86] Combine (store (v1i1 (scalar_to_vector (i8 X)))) -> (store (i8 X)).Craig Topper2018-03-041-0/+10
| | | | llvm-svn: 326670
* [X86] Lower v1i1/v2i1/v4i1/v8i1 load/stores to i8 load/store during op ↵Craig Topper2018-03-042-32/+66
| | | | | | | | legalization if AVX512DQ is not supported. We were previously doing this with isel patterns. Moving it to op legalization gives us chance to see the required bitcast earlier. And it lets us remove some isel patterns. llvm-svn: 326669
* [X86] This bit-test TODO has been moved in PR36551Simon Pilgrim2018-03-031-24/+0
| | | | llvm-svn: 326658
* [X86] Remove 'else' after return. NFCCraig Topper2018-03-031-3/+3
| | | | llvm-svn: 326642
* [Hexagon] Generate valignb for shifting shuffles (instead of vdelta)Krzysztof Parzyszek2018-03-021-11/+35
| | | | llvm-svn: 326627
* [RISCV] Implement MC relaxations for compressed instructions.Sameer AbuAsal2018-03-021-7/+80
| | | | | | | | | | | | | | | | | | Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
* [WebAssembly] Avoid cast ExprType to wasm::ValTypeSam Clegg2018-03-021-31/+30
| | | | | | | | | | | This cast was causing invalid signatures to be written for libcall functions. Add an MC test which includes a call to builtin memcpy. Differential Revision: https://reviews.llvm.org/D44037 llvm-svn: 326618
* Reland "[WebAssembly] More uses of uint8_t for single byte values"Heejin Ahn2018-03-022-14/+14
| | | | | | | | | | | | | | Summary: Original change was D43991 (rL326541) and was reverted by rL326571 and rL326572. This adds also the necessary MCCodeEmitter patch. Reviewers: sbc100 Subscribers: jfb, dschuff, sbc100, jgravelle-google, sunfish, llvm-commits, ncw Differential Revision: https://reviews.llvm.org/D44034 llvm-svn: 326614
* [SystemZ] Allow LRV/STRV with volatile memory accessesUlrich Weigand2018-03-021-6/+1
| | | | | | | | The byte-swapping loads and stores do not actually perform multiple accesses to their memory operand, so they are OK to use with volatile memory operands as well. Remove overly cautious check. llvm-svn: 326613
* [SystemZ] Add support for anyregcc calling conventionUlrich Weigand2018-03-023-12/+44
| | | | | | | | | | | | | This adds back-end support for the anyregcc calling convention for use with patchpoints. Since all registers are considered call-saved with anyregcc (except for 0 and 1 which may still be clobbered by PLT stubs and the like), this required adding support for saving and restoring vector registers in prologue/epilogue code for the first time. This is not used by any other calling convention. llvm-svn: 326612
* [SystemZ] Support stackmaps and patchpointsUlrich Weigand2018-03-024-1/+157
| | | | | | | This adds back-end support for the @llvm.experimental.stackmap and @llvm.experimental.patchpoint intrinsics. llvm-svn: 326611
* [SystemZ] Fix common-code users of stack sizeUlrich Weigand2018-03-022-47/+11
| | | | | | | | | | | | | | | | | | | On SystemZ we need to provide a register save area of 160 bytes to any called function. This size needs to be added when allocating stack in the function prologue. However, it was not accounted for as part of MachineFrameInfo::getStackSize(); instead the back-end used a private routine getAllocatedStackSize(). This is OK for code-gen purposes, but it breaks other users of the getStackSize() routine, in particular it breaks the recently- added -stack-size-section feature. Fix this by updating the main stack size tracked by common code (in emitPrologue) instead of using the private routine. No change in code generation intended. llvm-svn: 326610
* [SystemZ] Support vector registers in inline asmUlrich Weigand2018-03-022-9/+36
| | | | | | | | This adds support for specifying vector registers for use with inline asm statements, either via the 'v' constraint or by explicit register names (v0 ... v31). llvm-svn: 326609
* [Hexagon] Handle VACOPY in isel loweringKrzysztof Parzyszek2018-03-021-0/+1
| | | | llvm-svn: 326599
* [X86][BTVER2] Fix throughput of YMM bitwise instructionsSimon Pilgrim2018-03-021-0/+20
| | | | | | | | These instructions are double-pumped, split into 2 128-bit ops and then passing through either FPU pipe. Found while testing llvm-mca (D43951) llvm-svn: 326597
* [X86] Reject xmm16-31 in inline asm constraints when AVX512 is disabledCraig Topper2018-03-021-0/+9
| | | | | | | | Fixes PR36532 Differential Revision: https://reviews.llvm.org/D43960 llvm-svn: 326596
* [X86][x32] Save callee-save register used as base pointer for x32 ABIDerek Schuff2018-03-021-2/+6
| | | | | | | | | | | | | For the x32 ABI, since the base pointer register (EBX) is a callee save register it should be saved before use. This fixes https://bugs.llvm.org/show_bug.cgi?id=36011 Differential Revision: https://reviews.llvm.org/D42358 Patch by Pratik Bhatu llvm-svn: 326593
* [ARM] Fold variable into assert.Benjamin Kramer2018-03-021-2/+1
| | | | | | Avoids unused variable warnings in Release mode. llvm-svn: 326592
* AMDGPU/GlobalISel: InstrMapping for G_ZEXTMatt Arsenault2018-03-021-0/+20
| | | | llvm-svn: 326589
* AMDGPU/GlobalISel: InstrMapping for G_TRUNCMatt Arsenault2018-03-021-0/+10
| | | | llvm-svn: 326588
* AMDGPU/GlobalISel: Define InstrMappings for G_FCMPMatt Arsenault2018-03-021-0/+9
| | | | | | Patch by Tom Stellard llvm-svn: 326587
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.minnumMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326586
* [ARM] Fix access to stack arguments when re-aligning SP in Armv6mMomchil Velikov2018-03-022-17/+8
| | | | | | | | | | | | | | | | | | | | When an Armv6m function dynamically re-aligns the stack, access to incoming stack arguments (and to stack area, allocated for register varargs) is done via SP, which is incorrect, as the SP is offset by an unknown amount relative to the value of SP upon function entry. This patch fixes it, by making access to "fixed" frame objects be done via FP when the function needs stack re-alignment. It also changes the access to "fixed" frame objects be done via FP (instead of using R6/BP) also for the case when the stack frame contains variable sized objects. This should allow more objects to fit within the immediate offset of the load instruction. All of the above via a small refactoring to reuse the existing `ARMFrameLowering::ResolveFrameIndexReference.` Differential Revision: https://reviews.llvm.org/D43566 llvm-svn: 326584
* [Power9] Add missing instructions to the Power 9 schedulerStefan Pintilie2018-03-021-8/+59
| | | | | | | Adding more instructions using InstRW so that we can move away from ItinRW and ultimately have a complete Power 9 scheduler. llvm-svn: 326578
* Test commit: Remove an extraneous space. NFCDavid Stenberg2018-03-021-1/+1
| | | | | | Test commit access. llvm-svn: 326573
* Revert "[WebAssembly] More uses of uint8_t" and "[WebAssembly] Update tests"Nicholas Wilson2018-03-021-13/+13
| | | | | | | | | | This reverts commits r326541 and r326571. The tests were correct, and were updated with incorrect expectations. The original commit was broken and should be reverted to get things back to a working state. llvm-svn: 326572
* [ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WBFlorian Hahn2018-03-023-16/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code generation of VLD3, VLD4, VST3 and VST4 with register writeback is broken due to 2 separate bugs: 1) VLD1d64TPseudoWB_register and VLD1d64QPseudoWB_register are missing rules to expand them to non pseudo MIR. These are selected for ARMISD::VLD3_UPD/VLD4_UPD with v1i64 vectors in SelectVLD. 2) Selection of the right VLD/VST instruction is broken for load and store of 3 and 4 v1i64 vectors. SelectVLD and SelectVST are called with MIR opcode for fixed writeback (ie increment is access size) and call getVLDSTRegisterUpdateOpcode() to select an opcode with register writeback if base register update is of a different size. Since getVLDSTRegisterUpdateOpcode() only knows about VLD1/VLD2/VST1/VST2 the call is currently conditional on the number of element in the vector. However, VLD1/VST1 is selected by SelectVLD/SelectVST's caller for load and stores of 3 or 4 v1i64 vectors. Therefore the opcode is not updated which later lead to a fixed writeback instruction being constructed with an extra operand for the register writeback. This patch addresses the two issues as follows: - it adds the necessary mapping from VLD1d64TPseudoWB_register and VLD1d64QPseudoWB_register to VLD1d64Twb_register and VLD1d64Qwb_register respectively. Like for the existing _fixed variants, the cost of these is bumped for unaligned access. - it changes the logic in SelectVLD and SelectVSD to call isVLDfixed and isVSTfixed respectively to decide whether the opcode should be updated. It also reworks the logic and comments for pushing the writeback offset operand and r0 operand to clarify the logic: writeback offset needs to be pushed if it's a register writeback, r0 needs to be pushed if not and the instruction is a VLD1/VLD2/VST1/VST2. Reviewers: rengolin, t.p.northover, samparker Reviewed By: samparker Patch by Thomas Preud'homme <thomas.preudhomme@arm.com> Differential Revision: https://reviews.llvm.org/D42970 llvm-svn: 326570
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.maxnumMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326567
* [X86] Remove old UNIMPLEMENTED listSimon Pilgrim2018-03-021-14/+0
| | | | | | All of these are implemented and have appropriate test coverage llvm-svn: 326553
* [WebAssembly] More uses of uint8_t for single byte valuesHeejin Ahn2018-03-021-13/+13
| | | | | | | | | | | | Summary: It looks like this was missing from D43921. Reviewers: sbc100 Subscribers: jfb, dschuff, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D43991 llvm-svn: 326541
* AMDGPU/GCN: Promote i16 ctpopJan Vesely2018-03-022-0/+5
| | | | | | | | | i16 capable ASICs do not support i16 operands for this instruction. Add tablegen pattern to merge chained i16 additions. Differential Revision: https://reviews.llvm.org/D43985 llvm-svn: 326535
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOSIMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326534
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOUIMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326533
* AMDGPU/GlobalISel: Define instruction mapping for G_FMULMatt Arsenault2018-03-021-0/+1
| | | | llvm-svn: 326532
* AMDGPU/GlobalISel: Define instruction mapping for G_FADDMatt Arsenault2018-03-021-1/+3
| | | | | | Patch by Tom Stellard llvm-svn: 326526
* AMDGPU/GlobalISel: Define instruction mapping for G_SHLMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326525
* AMDGPU/GlobalISel: Define instruction mapping for G_XORMatt Arsenault2018-03-021-0/+1
| | | | llvm-svn: 326524
* AMDGPU/GlobalISel: Define instruction mapping for G_ANDMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326523
* [WebAssembly] Gather EH instructions in one place. NFC.Heejin Ahn2018-03-021-10/+20
| | | | | | | | | | | | | | | Summary: - Gather EH instructions in one place for easy tracking (more will be added later) - Variable name change Reviewers: dschuff Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D43742 llvm-svn: 326522
* bpf: introduce -mattr=dwarfris to disable DwarfUsesRelocationsAcrossSectionsYonghong Song2018-03-015-2/+16
| | | | | | | | | | | | | | | | | | | | | Commit e4507fb8c94b ("bpf: disable DwarfUsesRelocationsAcrossSections") disables MCAsmInfo DwarfUsesRelocationsAcrossSections unconditionally so that dwarf will not use cross section (between dwarf and symbol table) relocations. This new debug format enables pahole to dump structures correctly as libdwarves.so does not have BPF backend support yet. This new debug format, however, breaks bcc (https://github.com/iovisor/bcc) source debug output as llvm in-memory Dwarf support has some issues to handle it. More specifically, with DwarfUsesRelocationsAcrossSections disabled, JIT compiler does not generate .debug_abbrev and Dwarf DIE (debug info entry) processing is not happy about this. This patch introduces a new flag -mattr=dwarfris (dwarf relocation in section) to disable DwarfUsesRelocationsAcrossSections. DwarfUsesRelocationsAcrossSections is true by default. Signed-off-by: Yonghong Song <yhs@fb.com> llvm-svn: 326505
* [X86][MMX] Improve handling of 64-bit MMX constantsSimon Pilgrim2018-03-012-6/+29
| | | | | | | | | | | | 64-bit MMX constant generation usually ends up lowering into SSE instructions before being spilled/reloaded as a MMX type. This patch bitcasts the constant to a double value to allow correct loading directly to the MMX register. I've added MMX constant asm comment support to improve testing, it's better to always print the double values as hex constants as MMX is mainly an integer unit (and even with 3DNow! its just floats). Differential Revision: https://reviews.llvm.org/D43616 llvm-svn: 326497
* [Hexagon] Add trap1 instructionKrzysztof Parzyszek2018-03-014-0/+60
| | | | llvm-svn: 326492
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