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* add a case we fail to devirt.Chris Lattner2010-11-091-0/+20
| | | | llvm-svn: 118608
* Trailing whitespace.Jim Grosbach2010-11-091-6/+6
| | | | llvm-svn: 118606
* Further MCize ARM constant pool values. This allows basic PIC references forJim Grosbach2010-11-091-67/+83
| | | | | | object file emission. llvm-svn: 118601
* Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.Jim Grosbach2010-11-091-0/+2
| | | | llvm-svn: 118600
* For ARM load/store instructions, encode [reg+reg] with no shifter immediate asJim Grosbach2010-11-091-0/+3
| | | | | | a left shift by zero. llvm-svn: 118587
* ARM .word data fixups don't need an adjustment.Jim Grosbach2010-11-091-0/+1
| | | | llvm-svn: 118586
* Fix trailing whitespace and style, no functionality changeBruno Cardoso Lopes2010-11-091-170/+95
| | | | llvm-svn: 118515
* Add encoder method for ARM load/store shifted register offset operands.Jim Grosbach2010-11-093-1/+48
| | | | llvm-svn: 118513
* Add support for a few simple fixups to the ARM Darwin asm backend. This allowsJim Grosbach2010-11-092-10/+36
| | | | | | | | | | | | | | constant pool references and global variable refernces to resolve properly for object file generation. For example, int x; void foo(unsigned a, unsigned *p) { p[a] = x; } can now be successfully compiled directly to an (ARM mode) object file. llvm-svn: 118469
* Revert r118457 and r118458. These won't hold for GPRs.Bill Wendling2010-11-092-6/+8
| | | | llvm-svn: 118462
* Get the register and count from the register list operands.Bill Wendling2010-11-081-8/+5
| | | | llvm-svn: 118458
* reglist has two operands.Bill Wendling2010-11-081-0/+1
| | | | llvm-svn: 118457
* The "addRegListOperands()" function returns the start register and the totalBill Wendling2010-11-081-15/+21
| | | | | | number of registers in the list. llvm-svn: 118456
* Add support for ARM's specialized vector-compare-against-zero instructions.Owen Anderson2010-11-083-24/+68
| | | | llvm-svn: 118453
* Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka ↵Bruno Cardoso Lopes2010-11-083-12/+22
| | | | | | (ahatanaka@mips.com) llvm-svn: 118447
* Add "write back" bit encoding.Bill Wendling2010-11-081-8/+16
| | | | llvm-svn: 118446
* Fix PR8211Bruno Cardoso Lopes2010-11-081-0/+6
| | | | llvm-svn: 118445
* Adding working version of assembly parser for the MBlaze backendWesley Peck2010-11-0825-810/+498
| | | | | | Major cleanup of whitespace and formatting issues in MBlaze backend llvm-svn: 118434
* Revert 118422 in search of bot verdancy.Dale Johannesen2010-11-082-78/+10
| | | | llvm-svn: 118429
* Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.Jason W Kim2010-11-082-10/+78
| | | | llvm-svn: 118422
* Complete listing of ARM/MC/ELF relocation enumsJason W Kim2010-11-081-3/+134
| | | | llvm-svn: 118413
* Add generating function declaration for PTXChe-Liang Chiou2010-11-082-11/+129
| | | | llvm-svn: 118398
* Add physical register counting functionsChe-Liang Chiou2010-11-086-0/+176
| | | | llvm-svn: 118397
* Add a dummy PTXMCAsmStreamer classChe-Liang Chiou2010-11-084-0/+588
| | | | llvm-svn: 118396
* Make RegList an ASM operand so that TableGen will generate code for it. This isBill Wendling2010-11-081-2/+7
| | | | | | an initial implementation and may change once reglists are fully fleshed out. llvm-svn: 118390
* Revert.Bill Wendling2010-11-081-1/+1
| | | | llvm-svn: 118389
* Fix a README item: when doing a comparison with the resultDuncan Sands2010-11-071-12/+0
| | | | | | | | of a select instruction, see if doing the compare with the true and false values of the select gives the same result. If so, that can be used as the value of the comparison. llvm-svn: 118378
* In this context, a reglist is a reg.Bill Wendling2010-11-071-1/+1
| | | | llvm-svn: 118375
* implement aliases for div/idiv that have an explicit A register operand,Chris Lattner2010-11-061-0/+20
| | | | | | implementing rdar://8431864 llvm-svn: 118364
* Add support for parsing register lists. We can't use a bitfield to keep track ofBill Wendling2010-11-061-22/+64
| | | | | | | | | | | the registers, because the register numbers may be much greater than the number of bits available in the machine's register. I extracted the register list verification code out of the actual parsing of the registers. This made checking for errors much easier. It also limits the number of warnings that would be emitted for cascading infractions. llvm-svn: 118363
* add aliases for movs between seg registers and mem. There are multipleChris Lattner2010-11-061-0/+5
| | | | | | | | | | different forms of this instruction (movw/movl/movq) which we reported as being ambiguous. Since they all do the same thing, gas just picks the one with the shortest encoding. Follow its lead here. This implements rdar://8208615 llvm-svn: 118362
* move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.Chris Lattner2010-11-062-10/+18
| | | | llvm-svn: 118361
* Return the base register of a register list for the "getReg()" method. This isBill Wendling2010-11-061-3/+8
| | | | | | | to satisfy the ClassifyOperand method of the Asm matcher without having to add a RegList type to every back-end. llvm-svn: 118360
* work-in-progressChris Lattner2010-11-061-7/+6
| | | | llvm-svn: 118358
* General cleanup:Bill Wendling2010-11-061-36/+21
| | | | | | | - Make ARMOperand a class so that some things are internal to the class. - Reformatting. llvm-svn: 118357
* go to great lengths to work around a GAS bug my previous patchChris Lattner2010-11-062-8/+8
| | | | | | | | | | | | | | | | exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. llvm-svn: 118356
* rework the rotate-by-1 instructions to be defined like theChris Lattner2010-11-063-25/+46
| | | | | | | | | | | | | shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. llvm-svn: 118355
* change the fp comparison instructions to not have %st0 explicitlyChris Lattner2010-11-062-12/+9
| | | | | | | listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
* move the plethora of fp stack aliases to the .td file.Chris Lattner2010-11-062-39/+48
| | | | llvm-svn: 118353
* add (and document) the ability for alias results to haveChris Lattner2010-11-062-13/+16
| | | | | | | | fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). llvm-svn: 118352
* Add a RegList (register list) object to ARMOperand. It will be used soon to holdBill Wendling2010-11-061-1/+38
| | | | | | | (surprise!) a list of registers. Register lists are consecutive, so we only need to record the start register plus the number of registers. llvm-svn: 118351
* generalize alias support to allow the result of an alias toChris Lattner2010-11-062-21/+20
| | | | | | | add fixed immediate values. Move the aad and aam aliases to use this, and document it. llvm-svn: 118350
* move fnstsw aliases to .td file, fix typoChris Lattner2010-11-062-36/+6
| | | | llvm-svn: 118349
* move in/out aliases to the .td files.Chris Lattner2010-11-062-16/+16
| | | | llvm-svn: 118348
* move sldt, imul, and movabsq aliases from c++ to .td file.Chris Lattner2010-11-062-29/+18
| | | | llvm-svn: 118347
* correct suffix matching to search for s/l/t suffixes on Chris Lattner2010-11-061-33/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | floating point stack instructions instead of looking for b/w/l/q. This fixes issues where we'd accidentally match fistp to fistpl, when it is in fact an ambiguous instruction. This changes the behavior of llvm-mc to reject fstp, which was the correct fix for rdar://8456389: t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt') fstp (%rax) it also causes us to correctly reject fistp and fist, which addresses PR8528: t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl') fistp (%rax) ^ t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl') fist (%rax) ^ Thanks to Ismail Donmez for tracking down the issue here! llvm-svn: 118346
* Fix grammar.Bill Wendling2010-11-061-1/+1
| | | | llvm-svn: 118341
* Fix grammar.Bill Wendling2010-11-061-3/+3
| | | | llvm-svn: 118340
* MatchRegisterName() returns 0 if it can't match the register.Bill Wendling2010-11-061-2/+2
| | | | llvm-svn: 118339
* Use TryParseRegister() instead of MatchRegisterName(). The former returns -1Bill Wendling2010-11-061-5/+2
| | | | | | while the latter doesn't. llvm-svn: 118338
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