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* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-267-50/+163
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* Update generated code to use new API of GetElementPtrInst::Create.Nicolas Geoffray2011-07-261-2/+1
| | | | llvm-svn: 136138
* Fix over-zealous rename from r136095.Jim Grosbach2011-07-261-3/+3
| | | | llvm-svn: 136132
* ARM diagnostics for ldrexd/stredx out of order paired register operands.Jim Grosbach2011-07-261-1/+39
| | | | llvm-svn: 136110
* Remove now unused patterns. 0 insertions(+), 98 deletions(-)Bruno Cardoso Lopes2011-07-261-98/+0
| | | | llvm-svn: 136109
* Cleanup old matching for PUNPCK* variantsBruno Cardoso Lopes2011-07-261-44/+42
| | | | llvm-svn: 136108
* ARM fix for LDREX source register encoding.Jim Grosbach2011-07-261-2/+2
| | | | | | rdar://9842203 llvm-svn: 136102
* ARM assembly parsing and encoding for SWP[B] instructions.Jim Grosbach2011-07-262-6/+6
| | | | llvm-svn: 136098
* ARM SWP instructions store, too, not just load.Jim Grosbach2011-07-261-5/+3
| | | | llvm-svn: 136096
* Clean up the ARM asm parser a bit.Jim Grosbach2011-07-263-93/+95
| | | | | | | No intendeded functional change. Just cleaning up a bit to make things more self-consistent in layout and style. llvm-svn: 136095
* ARM fix asm parsing range check for [0,31] immediates.Jim Grosbach2011-07-261-1/+3
| | | | llvm-svn: 136091
* ARM parsing and encoding for SVC instruction.Jim Grosbach2011-07-263-4/+25
| | | | llvm-svn: 136090
* The compact unwinding offsets are divided by 8 on 64-bit machines.Bill Wendling2011-07-261-2/+4
| | | | llvm-svn: 136065
* Add 256-bit isel for movsldup/movshdupBruno Cardoso Lopes2011-07-261-21/+28
| | | | llvm-svn: 136051
* More movsldup/movshdup cleanup. Rewrite the mask matching function and addBruno Cardoso Lopes2011-07-262-37/+44
| | | | | | support for 256-bit versions (but no instruction selection yet, coming next). llvm-svn: 136050
* More cleanup, subtarget info isn't used here.Bruno Cardoso Lopes2011-07-261-8/+5
| | | | llvm-svn: 136049
* Add 128-bit AVX versions of movshdup/mosldupBruno Cardoso Lopes2011-07-261-0/+11
| | | | llvm-svn: 136048
* Cleanup movsldup/movshdup matching.Bruno Cardoso Lopes2011-07-262-62/+27
| | | | | | 27 insertions(+), 62 deletions(-) llvm-svn: 136047
* Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to ↵Evan Cheng2011-07-264-24/+24
| | | | | | createMCObjectStreamer. llvm-svn: 136031
* Remove a file from CMakeLists.txt that Evan removed in r136027.Chandler Carruth2011-07-261-1/+0
| | | | llvm-svn: 136030
* Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to ↵Evan Cheng2011-07-2616-49/+45
| | | | | | MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser. llvm-svn: 136027
* Clean up a pile of hacks in our CMake build relating to TableGen.Chandler Carruth2011-07-2639-13/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first problem to fix is to stop creating synthetic *Table_gen targets next to all of the LLVM libraries. These had no real effect as CMake specifies that add_custom_command(OUTPUT ...) directives (what the 'tablegen(...)' stuff expands to) are implicitly added as dependencies to all the rules in that CMakeLists.txt. These synthetic rules started to cause problems as we started more and more heavily using tablegen files from *subdirectories* of the one where they were generated. Within those directories, the set of tablegen outputs was still available and so these synthetic rules added them as dependencies of those subdirectories. However, they were no longer properly associated with the custom command to generate them. Most of the time this "just worked" because something would get to the parent directory first, and run tablegen there. Once run, the files existed and the build proceeded happily. However, as more and more subdirectories have started using this, the probability of this failing to happen has increased. Recently with the MC refactorings, it became quite common for me when touching a large enough number of targets. To add insult to injury, several of the backends *tried* to fix this by adding explicit dependencies back to the parent directory's tablegen rules, but those dependencies didn't work as expected -- they weren't forming a linear chain, they were adding another thread in the race. This patch removes these synthetic rules completely, and adds a much simpler function to declare explicitly that a collection of tablegen'ed files are referenced by other libraries. From that, we can add explicit dependencies from the smaller libraries (such as every architectures Desc library) on this and correctly form a linear sequence. All of the backends are updated to use it, sometimes replacing the existing attempt at adding a dependency, sometimes adding a previously missing dependency edge. Please let me know if this causes any problems, but it fixes a rather persistent and problematic source of build flakiness on our end. llvm-svn: 136023
* Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to ↵Evan Cheng2011-07-2515-62/+52
| | | | | | createMCAsmBackend. llvm-svn: 136010
* ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach2011-07-255-6/+32
| | | | llvm-svn: 136006
* Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128Bruno Cardoso Lopes2011-07-254-13/+58
| | | | | | This also fixes PR10452 llvm-svn: 136004
* Add remaining 256-bit vector bitcasts. This also fixes PR10451Bruno Cardoso Lopes2011-07-251-4/+18
| | | | llvm-svn: 136003
* - Handle special scalar_to_vector case: splats. Using a native 128-bitBruno Cardoso Lopes2011-07-254-1/+65
| | | | | | | | | | shuffle before inserting on a 256-bit vector. - Add AVX versions of movd/movq instructions - Introduce a few COPY patterns to match insert_subvector instructions. This turns a trivial insert_subvector instruction into a register copy, coalescing the xmm into a ymm and avoid emiting on more instruction. llvm-svn: 136002
* Reintroduce r135730, this is indeed the right approach, there is noBruno Cardoso Lopes2011-07-251-0/+18
| | | | | | native 256-bit vector instruction to do scalar_to_vector. llvm-svn: 136001
* Add a note about efficient codegen for binary log.Benjamin Kramer2011-07-251-0/+48
| | | | llvm-svn: 135996
* ARM assembly parsing and encoding for SSAT instruction.Jim Grosbach2011-07-256-63/+122
| | | | | | | | | | | | Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
* Refactoring fail.Evan Cheng2011-07-255-49/+47
| | | | llvm-svn: 135986
* Move CBackend and CppBackend MC initialization to TargetInfo.Evan Cheng2011-07-254-4/+4
| | | | llvm-svn: 135982
* Get rid of an incorrect optimization for shuffles with PALIGNR and simplify ↵Eli Friedman2011-07-251-15/+5
| | | | | | | | isPALIGNRMask. Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle. llvm-svn: 135980
* Fix more MC layering violations.Evan Cheng2011-07-251-2/+9
| | | | llvm-svn: 135979
* More MC layering violations.Evan Cheng2011-07-254-62/+59
| | | | llvm-svn: 135978
* Add LLVMAddTargetLibraryInfo to the C API.Rafael Espindola2011-07-251-0/+6
| | | | llvm-svn: 135975
* Separate MCInstPrinter registration from AsmPrinter registration.Evan Cheng2011-07-2512-65/+81
| | | | llvm-svn: 135974
* Simply ARM so_reg MIOperandInfo definitions.Jim Grosbach2011-07-251-4/+4
| | | | | | | | The shift immediate encoding, printing, etc. is handled directly by the enclosing operand definition, so it should be a vanilla immediate, not a nested complex operand (shift_imm). llvm-svn: 135968
* Fix last bits of MC layer issues. llvm-mc doesn't need to initialize ↵Evan Cheng2011-07-253-28/+12
| | | | | | TargetMachine's anymore. llvm-svn: 135963
* ARM asm operand renaming. Make things a bit more explicit.Jim Grosbach2011-07-252-32/+32
| | | | llvm-svn: 135959
* More simple cleanup of ARM asm operand definitions.Jim Grosbach2011-07-252-28/+13
| | | | llvm-svn: 135958
* Code clean up.Evan Cheng2011-07-255-23/+1
| | | | llvm-svn: 135954
* Refactor MBlaze target to separate MC routines from Target routines.Evan Cheng2011-07-2515-190/+216
| | | | llvm-svn: 135953
* Update the comment. This feature is available only on Darwin at the moment. ↵Bill Wendling2011-07-251-1/+2
| | | | | | Though it's not Darwin-specific. llvm-svn: 135951
* Make assembly parser method names more consistent.Jim Grosbach2011-07-253-28/+28
| | | | llvm-svn: 135950
* Unbreak the build.Oscar Fuentes2011-07-251-0/+1
| | | | llvm-svn: 135949
* Tidy up formatting.Jim Grosbach2011-07-251-50/+18
| | | | | | | | Remove some inititalizers that are the same as the default, move defs next to their (singular) uses and generally simplify some formatting of asm operand definitions. llvm-svn: 135946
* Tidy up a bit.Jim Grosbach2011-07-251-8/+2
| | | | llvm-svn: 135945
* Missed a file.Evan Cheng2011-07-251-0/+70
| | | | llvm-svn: 135943
* Refactor PPC target to separate MC routines from Target routines.Evan Cheng2011-07-2514-97/+57
| | | | llvm-svn: 135942
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