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* ARM64: always use i64 for the RHS of shift operationsTim Northover2014-04-033-81/+67
| | | | | | | | | | Switching between i32 and i64 based on the LHS type is a good idea in theory, but pre-legalisation uses i64 regardless of our choice, leading to potential ISel errors. Should fix PR19294. llvm-svn: 205519
* ARM: Use __STACK_LIMIT symbol for segmented stacksOliver Stannard2014-04-031-1/+1
| | | | | | | We cannot use STACK_LIMIT, as it is not reserved for the compiler by the C spec. llvm-svn: 205516
* ARM64: don't generate __sincos_stret calls unless on MachOTim Northover2014-04-031-5/+10
| | | | | | This should fix PR19314. llvm-svn: 205514
* [X86] As per suggestion from Craig Topper and Hal Finkel, overrideLang Hames2014-04-022-40/+39
| | | | | | | | | TargetInstrInfo::findCommutedOpIndices to enable VFMA*231 commutation, rather than abusing commuteInstruction. Thanks very much for the suggestion guys! llvm-svn: 205489
* [PowerPC] Make PPCTTI::getMemoryOpCost call BasicTTI::getMemoryOpCostHal Finkel2014-04-021-3/+3
| | | | | | | | | | PPCTTI::getMemoryOpCost will now make use of BasicTTI::getMemoryOpCost to calculate the base cost of the memory access, and then adjust on top of that. There is no functionality change from this modification, but it will become important so that PPCTTI can take advantage of scalarization information for which BasicTTI::getMemoryOpCost will account in the near future. llvm-svn: 205476
* [X86] Make the VFMA*231 variants commutable and relax the alignment restrictionsLang Hames2014-04-022-106/+147
| | | | | | | | | | | on FMA3 memory operands. FMA3 instructions are VEX encoded, so they can load from unaligned memory. Testcase to follow, along with related patch. <rdar://problem/16478629> llvm-svn: 205472
* Add comments and test case for [X86TTI] Make constant base pointers for ↵Juergen Ributzka2014-04-021-0/+3
| | | | | | GetElementPtr opaque (r204739). llvm-svn: 205468
* ARM: update subtarget information for Windows on ARMSaleem Abdulrasool2014-04-026-12/+83
| | | | | | | Update the subtarget information for Windows on ARM. This enables using the MC layer to target Windows on ARM. llvm-svn: 205459
* Make a few more range-based loops use explicit types.Jim Grosbach2014-04-022-2/+2
| | | | | | No functional change. llvm-svn: 205458
* TargetLibraryInfo: Disable memcpy and memset on R600Tom Stellard2014-04-021-1/+10
| | | | | | There are no implementations of these for R600. llvm-svn: 205455
* Simplify resolveFrameIndex() signature.Jim Grosbach2014-04-028-23/+14
| | | | | | | | Just pass a MachineInstr reference rather than an MBB iterator. Creating a MachineInstr& is the first thing every implementation did anyway. llvm-svn: 205453
* ARM: cortex-m0 doesn't support unaligned memory access.Jim Grosbach2014-04-021-1/+6
| | | | | | | | | | | | Unlike other v6+ processors, cortex-m0 never supports unaligned accesses. From the v6m ARM ARM: "A3.2 Alignment support: ARMv6-M always generates a fault when an unaligned access occurs." rdar://16491560 llvm-svn: 205452
* Make some range based loop types more explicit.Jim Grosbach2014-04-022-6/+6
| | | | | | No functional change, but more readable code. llvm-svn: 205451
* [mips] Add more Octeon cnMips instructionsKai Nacke2014-04-022-10/+43
| | | | | | | | | | | | Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
* [C++11,ARM64] Range based for and explicit 'override' in STP cleanup.Jim Grosbach2014-04-021-15/+13
| | | | | | No functional change intended. llvm-svn: 205446
* [C++11,ARM64] Range based for loops in constant promotion.Jim Grosbach2014-04-021-9/+6
| | | | | | No functional change intended. llvm-svn: 205445
* [C++11,ARM64] Range based for loops in load/store pair optimizer.Jim Grosbach2014-04-021-4/+1
| | | | | | No functional change intended. llvm-svn: 205444
* [C++11,ARM64] Range based for loops in target lowering.Jim Grosbach2014-04-021-3/+2
| | | | | | No functional change intended. llvm-svn: 205443
* [C++11,ARM64] Range based for loops in frame lowering.Jim Grosbach2014-04-021-5/+3
| | | | | | No functional change intended. llvm-svn: 205442
* [C++11,ARM64] Range based for loops in pseudo expansion.Jim Grosbach2014-04-021-3/+2
| | | | | | No functional change intended. llvm-svn: 205441
* [C++11,ARM64] Range based for loops for LOHJim Grosbach2014-04-021-34/+21
| | | | | | No functional change intended. llvm-svn: 205440
* [C++11,ARM64] Range based for loops TLS cleanup.Jim Grosbach2014-04-021-3/+2
| | | | | | No functional change intended. llvm-svn: 205439
* [C++11,ARM64] Range based for loops in branch relaxation.Jim Grosbach2014-04-021-6/+5
| | | | | | No functional change intended. llvm-svn: 205438
* [C++11,ARM64] Range based for loops in address type promotion.Jim Grosbach2014-04-021-34/+25
| | | | | | No functional change intended. llvm-svn: 205437
* [ARM64][CollectLOH] Remove the link to the radar from the comments.Quentin Colombet2014-04-021-3/+0
| | | | llvm-svn: 205435
* ARM: Add support for segmented stacksOliver Stannard2014-04-025-0/+378
| | | | | | Patch by Alex Crichton, ILyoan, Luqman Aden and Svetoslav. llvm-svn: 205430
* ARM64: use GOT for weak symbols & PIC.Tim Northover2014-04-021-6/+23
| | | | | | | | | | Weak symbols cannot use the small code model's usual ADRP sequences since the instruction simply may not be able to encode a value of 0. This redirects them to use the GOT, which hopefully linkers are able to cope with even in the static relocation model. llvm-svn: 205426
* ARM64: fix lowering of fp128 fptosi/fptouiTim Northover2014-04-021-1/+6
| | | | | | | We were creating libcall nodes that returned an MVT::f128, when these particular operations actually return an int of some stripe. llvm-svn: 205425
* ARM64: make sure first argument to INSERT_SUBVECTOR has right type.Tim Northover2014-04-021-1/+1
| | | | | | | | Again, coalescing and other optimisations swiftly made the MachineInstrs consistent again, but when compiled at -O0 a bad INSERT_SUBREGISTER was produced. llvm-svn: 205423
* ARM64: convert fp16 narrowing ISel to pseudo-instructionTim Northover2014-04-023-13/+14
| | | | | | | | The previous attempt was fine with optimisations, but was actually rather cavalier with its types. When compiled at -O0, it produced invalid COPY MachineInstrs. llvm-svn: 205422
* Mark FPB as a reserved register when needed.Job Noorman2014-04-021-1/+3
| | | | llvm-svn: 205421
* Remove duplicated DMB instructionsRenato Golin2014-04-024-0/+104
| | | | | | | | | ARM specific optimiztion, finding places in ARM machine code where 2 dmbs follow one another, and eliminating one of them. Patch by Reinoud Elhorst. llvm-svn: 205409
* Added isTargetWindowsMSVC(), renamed isTargetMingw() to isTargetWindowsGNU()Yaron Keren2014-04-022-10/+24
| | | | | | | | | and isTargetCygwin() to isTargetWindowsCygwin() to be consistent with the four Windows environments in Triple.h. Suggestion by Saleem Abdulrasool! llvm-svn: 205393
* [ARM64][CollectLOH] Add some comments to explain how the LOHsQuentin Colombet2014-04-021-1/+52
| | | | | | | framework works (for the compiler part), since the design document is not available. llvm-svn: 205379
* [PowerPC] Add some missing VSX bitcast patternsHal Finkel2014-04-011-0/+8
| | | | llvm-svn: 205352
* If isKnownWindowsMSVCEnvironment then getOS == Triple::Win32 andYaron Keren2014-04-012-3/+2
| | | | | | Environment == Triple::MSVC so it will never be MinGW or Cygwin. llvm-svn: 205349
* Implement X86TTI::getUnrollingPreferencesHal Finkel2014-04-011-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | This provides an initial implementation of getUnrollingPreferences for x86. getUnrollingPreferences is used by the generic (concatenation) unroller, which is distinct from the unrolling done by the loop vectorizer. Many modern x86 cores have some kind of uop cache and loop-stream detector (LSD) used to efficiently dispatch small loops, and taking full advantage of this requires unrolling small loops (small here means 10s of uops). These caches also have limits on the number of taken branches in the loop, and so we also cap the loop unrolling factor based on the maximum "depth" of the loop. This is currently calculated with a partial DFS traversal (partial because it will stop early if the path length grows too much). This is still an approximation, and one that is both conservative (because it does not account for branches eliminated via block placement) and optimistic (because it is only recording the maximum depth over minimum paths). Nevertheless, because the loops that fit in these uop caches are so small, it is not clear how much the details matter. The original set of patches posted for review produced the following test-suite performance results (from the TSVC benchmark) at that time: ControlLoops-dbl - 13% speedup ControlLoops-flt - 15% speedup Reductions-dbl - 7.5% speedup llvm-svn: 205348
* [mips] Add Octeon cnMips instructions mtmX and mtpXKai Nacke2014-04-012-0/+19
| | | | | | | | | Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px". Includes tests. Reviews by: Daniel.Sanders@imgtec.com llvm-svn: 205343
* Support segmented stacks on Win64Reid Kleckner2014-04-011-2/+5
| | | | | | | Identical to Win32 method except the GS segment register is used for TLS instead of FS and pvArbitrary is at TEB offset 0x28 instead of 0x14. llvm-svn: 205342
* isTargetWindows() renamed to isTargetKnownWindowsMSVC()Yaron Keren2014-04-016-16/+16
| | | | | | | | to reflect its current functionality. Based on Takumi NAKAMURA suggestion. llvm-svn: 205338
* ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ↵Christian Pirker2014-04-0110-114/+114
| | | | | | ThumbLE/ThumbBE llvm-svn: 205317
* ARM: teach LLVM that Cortex-A7 is very similar to A8.Tim Northover2014-04-013-9/+11
| | | | llvm-svn: 205314
* Attempting to fix r205124, which had failed asserts when built with MSVC.Aaron Ballman2014-04-011-1/+1
| | | | | | Suggestion from Yaron Keren. llvm-svn: 205313
* ARM: add cyclone CPU with ZeroCycleZeroing feature.Tim Northover2014-04-015-6/+45
| | | | | | | | The Cyclone CPU is similar to swift for most LLVM purposes, but does have two preferred instructions for zeroing a VFP register. This teaches LLVM about them. llvm-svn: 205309
* [mips] Renamed ParseAnyRegisterWithoutDollar to MatchAnyRegisterWithoutDollarDaniel Sanders2014-04-011-8/+14
| | | | | | | | | This is for consistency with other functions. The Parse* functions consume tokens and the Match* functions don't. No functional change. llvm-svn: 205305
* Fixing an MSVC warning about widening the result of a 32-bit shift ↵Aaron Ballman2014-04-011-1/+1
| | | | | | implicitly. No functional change intended. llvm-svn: 205304
* ARM64: add intrinsic for pmull (p64 x p64 = p128) operations.Tim Northover2014-04-011-0/+7
| | | | llvm-svn: 205302
* Fixing warnings in the MSVC build. No functional changes intended.Aaron Ballman2014-04-015-42/+42
| | | | llvm-svn: 205301
* [mips] Extend ParseJumpTarget to support the full symbol expression syntax.Daniel Sanders2014-04-011-27/+6
| | | | | | | | | | | | | | | | Summary: This should fix the issues the D3222 caused in lld. Testcase is based on the one that failed in the buildbot. Depends on D3233 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3234 llvm-svn: 205298
* [mips] Use AsmLexer::peekTok() to resolve the conflict between $reg and $symDaniel Sanders2014-04-011-15/+10
| | | | | | | | | | | | | | | Summary: Parsing registers no longer consume the $ token before it's confirmed whether it really has a register or not, therefore it's no longer impossible to match symbols if registers were tried first. Depends on D3232 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3233 llvm-svn: 205297
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