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* x86: add implicit defs for cpuidReid Kleckner2014-01-281-2/+7
| | | | | | | This avoids miscompiling MS inline asm in LLVM where we have to infer clobbers. Test case forthcoming in Clang. llvm-svn: 200279
* [TLI] Add a new hook to TargetLowering to query the target if a load of a ↵Juergen Ributzka2014-01-284-0/+35
| | | | | | | | | | | | | | | | | constant should be converted to simply the constant itself. Before this patch we used getIntImmCost from TargetTransformInfo to determine if a load of a constant should be converted to just a constant, but the threshold for this was set to an arbitrary value. This value works well for the two targets (X86 and ARM) that implement this target-hook, but it isn't target-independent at all. Now targets have the possibility to decide directly if this optimization should be performed. The default value is set to false to preserve the current behavior. The target hook has been moved to TargetLowering, which removed the last use and need of TargetTransformInfo in SelectionDAG. llvm-svn: 200271
* Revert r199871 and replace it with a simple check in the debug infoEric Christopher2014-01-2810-22/+23
| | | | | | | | | code to see if we're emitting a function into a non-default text section. This is still a less-than-ideal solution, but more contained than r199871 to determine whether or not we're emitting code into an array of comdat sections. llvm-svn: 200269
* ARM MC: Fix the initial DWARF CFI unwind info at the start of a functionMark Seaborn2014-01-271-2/+8
| | | | | | | | | | | | | | | | | | | | This brings MC into line with GNU 'as' on ARM, and it brings the ARM target into line with most other LLVM targets, which declare the initial CFI state with addInitialFrameState(). Without this, functions generated with .cfi_startproc/endproc on ARM will tend to cause GDB to abort with: gdb/dwarf2-frame.c:1132: internal-error: Unknown CFA rule. I've also tested this by comparing the output of "readelf -w" on the object files produced by llvm-mc and gas when given the .s file added here. This change is part of addressing PR18636. Differential Revision: http://llvm-reviews.chandlerc.com/D2597 llvm-svn: 200255
* Fix unsupported addressing mode assertion for pldDavid Peixotto2014-01-272-2/+6
| | | | | | | | | | | | | | | | | | | Summary: This commit gives an address mode to the PLD instruction. We were getting an assertion failure in the frame lowering code because we had code that was doing a pld of a stack allocated address. The frame lowering was checking the address mode and then asserting because pld had none defined. This commit fixes pld for arm mode. There was a previous fix for thumb mode in a separate commit. The commit for thumb mode added a test in a separate file because it would otherwise fail for arm. This commit moves the thumb test back into the prefetch.ll file and adds the corresponding arm test. Differential Revision: http://llvm-reviews.chandlerc.com/D2622 llvm-svn: 200248
* test commit: add minor commentGautam Chakrabarti2014-01-271-1/+1
| | | | llvm-svn: 200244
* XCore: Fix typo in function name.Benjamin Kramer2014-01-273-10/+10
| | | | llvm-svn: 200216
* R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructionsMichel Danzer2014-01-273-21/+101
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 200196
* R600/SI: Add intrinsic for S_SENDMSG instructionMichel Danzer2014-01-275-2/+54
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 200195
* Print .mask and .fmask with the target streamer.Rafael Espindola2014-01-274-22/+46
| | | | | | | Testing this also found the missing '\n' after .frame that this patch also fixes. llvm-svn: 200192
* Print .frame via the target streamer.Rafael Espindola2014-01-273-5/+21
| | | | llvm-svn: 200186
* [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or ↵Kevin Qin2014-01-272-29/+95
| | | | | | | | SHUFFLE_VECTOR. Replace r199791. llvm-svn: 200180
* Revert r199791.Kevin Qin2014-01-272-90/+29
| | | | | | It's old version which has some bugs. I'll commit lattest patch soon. llvm-svn: 200179
* Use SwitchSection in MipsAsmPrinter::EmitStartOfAsmFile.Rafael Espindola2014-01-271-16/+17
| | | | llvm-svn: 200178
* Remove dead code.Rafael Espindola2014-01-272-25/+0
| | | | llvm-svn: 200174
* Add back spaces I missed in the conversion to emitRawComments.Rafael Espindola2014-01-271-3/+3
| | | | | | Sorry about that. llvm-svn: 200171
* Use emitRawComment instead of EmitRawText.Rafael Espindola2014-01-271-4/+5
| | | | llvm-svn: 200170
* Add missing file.Rafael Espindola2014-01-271-0/+27
| | | | llvm-svn: 200169
* Add a XCoreTargetStreamer and port over the simple uses of EmitRawText.Rafael Espindola2014-01-262-9/+64
| | | | llvm-svn: 200167
* ARM: improve diagnostics for .word directiveSaleem Abdulrasool2014-01-261-1/+3
| | | | | | | | | If a complex expression was passed to the .word directive and the first part of the directive failed to parse, a secondary diagnostic would be produced that would clutter the error diagnostics. Improve the diagnostics by consuming the remainder of the statement. llvm-svn: 200160
* MC: whitespaceSaleem Abdulrasool2014-01-261-57/+56
| | | | | | Fix indentation, remove unnecessary line. NFC. llvm-svn: 200158
* Avoid C++ comment in C sourcesAlp Toker2014-01-261-1/+1
| | | | | | lib/Target/X86/Disassembler/X86DisassemblerDecoder.c:1361:7: error: C++ style comments are not allowed in ISO C90 llvm-svn: 200153
* Follow up of r200095. Code clean up.Evan Cheng2014-01-261-1/+1
| | | | llvm-svn: 200152
* Clean up the Legal/Expand logic for SPARC popc.Jakob Stoklund Olesen2014-01-262-5/+8
| | | | llvm-svn: 200141
* Implement the missing bits corresponding to .mips_hack_elf_flags.Rafael Espindola2014-01-265-86/+47
| | | | | | | | | | | | These were: * noreorder handling on the target object streamer and asm parser. * setting the initial flag bits based on the enabled features. * setting the elf header flag for micromips It is *really* depressing I am the one doing this instead of someone at mips actually taking the time to understand the infrastructure. llvm-svn: 200138
* Pass a MCSubtargetInfo down to the TargetStreamer creation.Rafael Espindola2014-01-268-1/+9
| | | | | | | With this the target streamers will be able to know the target features that are in use. llvm-svn: 200135
* Only generate the popc instruction for SPARC CPUs that implement it.Jakob Stoklund Olesen2014-01-264-6/+13
| | | | | | | The popc instruction is defined in the SPARCv9 instruction set architecture, but it was emulated on CPUs older than Niagara 2. llvm-svn: 200131
* Fix swapped CASA operands.Jakob Stoklund Olesen2014-01-261-2/+2
| | | | | | Found by SingleSource/UnitTests/AtomicOps.c llvm-svn: 200130
* Construct the MCStreamer before constructing the MCTargetStreamer.Rafael Espindola2014-01-2613-59/+83
| | | | | | | | | | This has a few advantages: * Only targets that use a MCTargetStreamer have to worry about it. * There is never a MCTargetStreamer without a MCStreamer, so we can use a reference. * A MCTargetStreamer can talk to the MCStreamer in its constructor. llvm-svn: 200129
* Convert some easy uses of EmitRawText to TargetStreamer methods.Rafael Espindola2014-01-263-12/+97
| | | | llvm-svn: 200122
* Improve some x86 type constraints.Craig Topper2014-01-261-11/+22
| | | | llvm-svn: 200120
* Improve pattern match from v1i8 to v1i32 for AArch64 Neon.Jiangning Liu2014-01-261-12/+22
| | | | llvm-svn: 200119
* Implement pattern match from v1xx to v1xx for AArch64 Neon.Jiangning Liu2014-01-261-0/+85
| | | | llvm-svn: 200113
* [AArch64 NEON] Add patterns for concat_vector on v2i32.Kevin Qin2014-01-261-2/+10
| | | | llvm-svn: 200111
* Set displacementSize to 1 for instrucitons with mod==0x1. Fixes PR17310. ↵Craig Topper2014-01-251-0/+3
| | | | | | Modified from patch by James Courtier-Dutton. llvm-svn: 200100
* Clean up hack which is no longer needed after r198617. No functionality change.Evan Cheng2014-01-251-3/+2
| | | | llvm-svn: 200095
* This reverts commit r200064 and r200051.Rafael Espindola2014-01-255-69/+42
| | | | | | | | | | | | | | | | | | | r200064 depends on r200051. r200051 is broken: I tries to replace .mips_hack_elf_flags, which is a good thing, but what it replaces it with is even worse. The new emitMipsELFFlags it adds corresponds to no assembly directive, is not marked as a hack and is not even printed to the .s file. The patch also introduces more uses of hasRawTextSupport. The correct way to remove .mips_hack_elf_flags is to have the mips target streamer handle the default flags (and command line options). That way the same code path is used for asm and obj. The streamer interface should *really* correspond to what is printed in the .s file. llvm-svn: 200078
* Remove an easy use of EmitRawText from PPC.Rafael Espindola2014-01-254-7/+19
| | | | | | This makes lib/Target/PowerPC EmitRawText free. llvm-svn: 200065
* Revert "Revert "Add Constant Hoisting Pass" (r200034)"Juergen Ributzka2014-01-252-1/+96
| | | | | | | This reverts commit r200058 and adds the using directive for ARMTargetTransformInfo to silence two g++ overload warnings. llvm-svn: 200062
* Revert "Add Constant Hoisting Pass" (r200034)Hans Wennborg2014-01-251-95/+0
| | | | | | | | | | | | | | | This commit caused -Woverloaded-virtual warnings. The two new TargetTransformInfo::getIntImmCost functions were only added to the superclass, and to the X86 subclass. The other targets were not updated, and the warning highlighted this by pointing out that e.g. ARMTTI::getIntImmCost was hiding the two new getIntImmCost variants. We could pacify the warning by adding "using TargetTransformInfo::getIntImmCost" to the various subclasses, or turning it off, but I suspect that it's wrong to leave the functions unimplemnted in those targets. The default implementations return TCC_Free, which I don't think is right e.g. for ARM. llvm-svn: 200058
* [Mips] TargetStreamer ELF flag Support for default and commandline options.Jack Carter2014-01-255-42/+69
| | | | | | | | | | | | | | | This patch uses a common MipsTargetSteamer interface for both MipsAsmPrinter and MipsAsmParser for recording default and commandline driven directives that affect ELF header flags. It has been noted that the .ll tests affected by this patch belong in test/Codegen/Mips. I will move them in a separate patch. Also, a number of directives do not get expressed by AsmPrinter in the resultant .s assembly such as setting the correct ASI. I have noted this in the tests and they will be addressed in later patches. llvm-svn: 200051
* [AArch64] Removed unused i8 type from FPR8 register class.Ana Pazos2014-01-241-1/+1
| | | | | | | | | | | | | | | The i8 type is not registered with any register class. This causes a segmentation fault in MachineLICM::getRegisterClassIDAndCost. The code selects the first type associated with register class FPR8, which happens to be i8. It uses this type (i8) to get the representative class pointer, which is 0. It then uses this pointer to access a field, resulting in segmentation fault. Since i8 type is not being used for printing any neon instruction we can safely remove it. llvm-svn: 200046
* Add Constant Hoisting PassJuergen Ributzka2014-01-241-0/+95
| | | | | | | | Retry commit r200022 with a fix for the build bot errors. Constant expressions have (unlike instructions) module scope use lists and therefore may have users in different functions. The fix is to simply ignore these out-of-function uses. llvm-svn: 200034
* Revert "Add Constant Hoisting Pass"Juergen Ributzka2014-01-241-95/+0
| | | | | | This reverts commit r200022 to unbreak the build bots. llvm-svn: 200024
* Add Constant Hoisting PassJuergen Ributzka2014-01-241-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass identifies expensive constants to hoist and coalesces them to better prepare it for SelectionDAG-based code generation. This works around the limitations of the basic-block-at-a-time approach. First it scans all instructions for integer constants and calculates its cost. If the constant can be folded into the instruction (the cost is TCC_Free) or the cost is just a simple operation (TCC_BASIC), then we don't consider it expensive and leave it alone. This is the default behavior and the default implementation of getIntImmCost will always return TCC_Free. If the cost is more than TCC_BASIC, then the integer constant can't be folded into the instruction and it might be beneficial to hoist the constant. Similar constants are coalesced to reduce register pressure and materialization code. When a constant is hoisted, it is also hidden behind a bitcast to force it to be live-out of the basic block. Otherwise the constant would be just duplicated and each basic block would have its own copy in the SelectionDAG. The SelectionDAG recognizes such constants as opaque and doesn't perform certain transformations on them, which would create a new expensive constant. This optimization is only applied to integer constants in instructions and simple (this means not nested) constant cast experessions. For example: %0 = load i64* inttoptr (i64 big_constant to i64*) Reviewed by Eric llvm-svn: 200022
* Add final and owerride keywords to TargetTransformInfo's subclasses.Juergen Ributzka2014-01-245-50/+56
| | | | llvm-svn: 200021
* Fix known typosAlp Toker2014-01-2438-50/+52
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* Unify duplicated functions.Rafael Espindola2014-01-243-21/+5
| | | | llvm-svn: 200014
* Move emitInlineAsmEnd to the AsmPrinter interface.Rafael Espindola2014-01-243-17/+19
| | | | | | | | There is no inline asm in a .s file. Therefore, there should be no logic to handle it in the streamer. Inline asm only exists in bitcode files, so the logic can live in the (long misnamed) AsmPrinter class. llvm-svn: 200011
* [AArch64 NEON] Fix a bug in implementing register copy bwtween FPR16.Kevin Qin2014-01-241-2/+2
| | | | llvm-svn: 199978
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