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* [ARM] Enable spilling of the hGPR register class in Thumb2Petr Pavlu2018-11-081-6/+2
| | | | | | | | | | Generalize code in Thumb2InstrInfo::storeRegToStackSlot() and loadRegToStackSlot() to allow the GPR class or any of its sub-classes (including hGPR) to be stored/loaded by ARM::t2STRi12/ARM::t2LDRi12. Differential Revision: https://reviews.llvm.org/D51927 llvm-svn: 346401
* [MSP430] Fix encodeInstruction() for big endian hostsAnton Korobeynikov2018-11-081-4/+3
| | | | | | | | | | Reviewers: asl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54251 llvm-svn: 346391
* [WebAssembly] Add V128 to WebAssemblyInstrInfo::copyPhysRegThomas Lively2018-11-081-0/+2
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53872 llvm-svn: 346384
* [AMDGPU] Extend promote alloca vectorizationStanislav Mekhanoshin2018-11-081-4/+20
| | | | | | | | | | | Promote alloca can vectorize a small array by bitcasting it to a vector type. Extend vectorization for the case when alloca is already a vector type. We still want to replace GEPs with an insert/extract element instructions in this case. Differential Revision: https://reviews.llvm.org/D54219 llvm-svn: 346376
* [MSP430] Add MC layerAnton Korobeynikov2018-11-0829-1092/+2685
| | | | | | | | | | | | | | | | | Summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Reviewers: asl Reviewed By: asl Subscribers: pftbest, krisb, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D53661 llvm-svn: 346374
* [AArch64] [Windows] Address post-commit review comment on r346358.Eli Friedman2018-11-071-1/+2
| | | | | | | | In this context, usesWindowsCFI() is basically the same thing as isOSWindows(), but it makes the relevant property of the target more explicit. llvm-svn: 346366
* Revert "AMDGPU: Divergence-driven selection of scalar buffer load intrinsics"Nicolai Haehnle2018-11-076-90/+220
| | | | | | | | This reverts commit r344696 for now (except for some test additions). See https://bugs.freedesktop.org/show_bug.cgi?id=108611. llvm-svn: 346364
* AMDGPU/InsertWaitcnts: Cleanup some old cruft (NFCI)Nicolai Haehnle2018-11-071-91/+71
| | | | | | | | | | | | Summary: Remove redundant logic and simplify control flow. Reviewers: msearles, rampitec, scott.linder, kanarayan Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D54086 llvm-svn: 346363
* AMDGPU/InsertWaitcnts: Remove kill-related logicNicolai Haehnle2018-11-071-101/+1
| | | | | | | | | | | | | | | | Summary: This is not needed, because we don't actually insert relevant branches for KILLs that late in the compilation flow. Besides, this was always checking for the wrong kill opcode anyway... Reviewers: msearles, rampitec, scott.linder, kanarayan Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D54085 llvm-svn: 346362
* AMDGPU/NFC: Split FLAT_Global_Atomic_Pseudo into RTN/NO_RTN multiclassesKonstantin Zhuravlyov2018-11-071-11/+30
| | | | llvm-svn: 346361
* [AArch64] [Windows] Trap after noreturn calls.Eli Friedman2018-11-071-0/+10
| | | | | | | | | Like the comment says, this isn't the most efficient fix in terms of codesize, but it works. Differential Revision: https://reviews.llvm.org/D54129 llvm-svn: 346358
* AMDGPU/NFC: Split MUBUF_Pseudo_Atomics into RTN/NO_RTN multiclassesKonstantin Zhuravlyov2018-11-071-5/+16
| | | | llvm-svn: 346357
* [ARM] Fix CPSR liveness in tMOVCCr_pseudo lowering.Eli Friedman2018-11-071-0/+44
| | | | | | | | | | | | | | | | | | | | | The lowering was missing live-ins in certain cases, like a sequence of multiple tMOVCCr_pseudo instructions. This would lead to a verifier failure, and on pre-v6 Thumb CPSR would be incorrectly clobbered. For reasons I don't completely understand, it's hard to get a sequence of multiple tMOVCCr_pseudo instructions; the issue only seems to show up with 64-bit comparisons where the result is zero-extended. I added some extra testcases in case that changes in the future. Probably some optimization opportunities here if anyone is interested. (@test_slt_not is the case that was getting miscompiled.) The code to check the liveness of CPSR was stolen from X86ISelLowering.cpp; maybe it could be refactored into common helper, but I have no idea where to put it. Differential Revision: https://reviews.llvm.org/D54192 llvm-svn: 346355
* Allow subclassing ExternalAAMatt Arsenault2018-11-074-7/+24
| | | | | | | | | | | | | | This allows testing AMDGPU alias analysis like any other alias analysis pass. This fixes the existing test pointlessly running opt -O3 when it really just wants to run the one analysis. Before there was no way to test this using -aa-eval with opt, since the default constructed pass is run. The wrapper subclass allows the default constructor to pass the necessary callback. llvm-svn: 346353
* [X86] improve split-stack machine BB placementThan McIntosh2018-11-071-2/+2
| | | | | | | | | | | | | | | Summary: The conditional branch created to support -fsplit-stack for X86 is left unbiased/unhinted, resulting in less than ideal block placement: the __morestack call block is kept on the main hot path. Bias the branch to insure that the stack allocation block is treated as a "cold" block during machine basic block placement. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54123 llvm-svn: 346336
* fix typos aggressively; NFCSanjay Patel2018-11-072-2/+2
| | | | llvm-svn: 346316
* [X86][FixupLEA] Avoid checking target features for every single processed ↵Andrea Di Biagio2018-11-071-18/+24
| | | | | | instruction. NFCI llvm-svn: 346309
* [MIPS GlobalISel] Set operand order for G_MERGE and G_UNMERGEPetar Avramovic2018-11-073-9/+9
| | | | | | | | | Set operands order for G_MERGE_VALUES and G_UNMERGE_VALUES so that least significant bits always go first, regardless of endianness. Differential Revision: https://reviews.llvm.org/D54098 llvm-svn: 346305
* [PATCH] [AArch64] Refactor helper functions (NFC)Evandro Menezes2018-11-062-8/+8
| | | | | | Refactor helper functions in AArch64InstrInfo to be static methods. llvm-svn: 346273
* AMDGPU: Add an option -disable-promote-alloca-to-ldsYaxun Liu2018-11-061-0/+8
| | | | | | | | | | Add this option for debugging and providing workaround. By default it is off so no behavior change in backend. Differential Revision: https://reviews.llvm.org/D54158 llvm-svn: 346267
* [X86] Add custom promotion of v2i8/v2i16 fp_to_sint to avoid over promotion ↵Craig Topper2018-11-061-1/+24
| | | | | | to v2i64 which would force scalarization. llvm-svn: 346259
* LivePhysRegs/IfConversion: Change some types from unsigned to MCPhysReg; NFCMatthias Braun2018-11-063-3/+3
| | | | | | | | Change the type in a couple of lists and sets that only store physical registers from unsigned to MCPhysRegs. The later is only 16bits and saves us a bit of memory. llvm-svn: 346254
* [mips] Support sigrie instructionSimon Atanasyan2018-11-066-1/+47
| | | | | | | | | The `sigrie` instruction signals a Reserved Instruction Exception. This patch adds support for assembling / disassembling the instruction. Differential Revision: http://reviews.llvm.org/D53861 llvm-svn: 346230
* [X86][NFC] Fix comment.Clement Courbet2018-11-061-4/+4
| | | | llvm-svn: 346226
* AArch64: Cleanup CCMP code; NFCMatthias Braun2018-11-061-29/+30
| | | | | | | | | | Cleanup CCMP pattern matching code in preparation for review/bugfix: - Rename `isConjunctionDisjunctionTree()` to `canEmitConjunction()` (it won't accept arbitrary disjunctions and is really about whether we can transform the subtree into a conjunction that we can emit). - Rename `emitConjunctionDisjunctionTree()` to `emitConjunction()` llvm-svn: 346203
* Revert "[WebAssembly] Fixup `main` signature by default"Sam Clegg2018-11-061-1/+6
| | | | | | | | | | This reverts rL345880. It caused some test failures on the webassembly waterfall. e.g. binaryen2.test_mainenv fails due the fact that `envp` ends up being undef rather than 0. Differential Revision: https://reviews.llvm.org/D54117 llvm-svn: 346187
* MachineFunction: Store more specific reference to LLVMTargetMachine; NFCMatthias Braun2018-11-051-1/+1
| | | | | | | | | | MachineFunction can only be used in code using lib/CodeGen, hence we can keep a more specific reference to LLVMTargetMachine rather than just TargetMachine around. Do the same for references in ScheduleDAG and RegUsageInfoCollector. llvm-svn: 346183
* [TargetLowering] Change TargetLoweringBase::getPreferredVectorAction to take ↵Craig Topper2018-11-0513-18/+17
| | | | | | | | an MVT instead of an EVT. NFC The main caller of this already has an MVT and several targets called getSimpleVT inside without checking isSimple. This makes the simpleness explicit. llvm-svn: 346180
* AMDGPU: Add sram-ecc featureKonstantin Zhuravlyov2018-11-056-21/+27
| | | | | | Differential Revision: https://reviews.llvm.org/D53222 llvm-svn: 346177
* [X86] Don't turn any_extend from a mask register into a sign_extend during ↵Craig Topper2018-11-052-2/+14
| | | | | | | | | | lowering. Add patterns to match any_extend during isel instead. SimplifyDemandedBits can turn a sign_extend back into an any_extend and trigger an infinite loop. So instead legalize it the same way as a sign_extend, but preserve the opcode. Then just pattern match it the same as sign_extend during isel. I don't have a reduced test case for such an infinite loop yet. llvm-svn: 346170
* [Power9] Add support for stxvw4x.be and stxvd2x.be intrinsicsZaara Syeda2018-11-051-4/+4
| | | | | | | | | | | | On Power9, we don't have patterns to select the following intrinsics: llvm.ppc.vsx.stxvw4x.be llvm.ppc.vsx.stxvd2x.be This patch adds support for these. Differential Revision: https://reviews.llvm.org/D53581 llvm-svn: 346148
* [Mips] Supplement long branch pseudo instructionsStefan Maksimovic2018-11-055-11/+32
| | | | | | | | | | | Expand on LONG_BRANCH_LUi and LONG_BRANCH_(D)ADDiu pseudo instructions by creating variants which support less operands/accept GPR64Opnds as their operand in order to appease the machine verifier pass. Differential Revision: https://reviews.llvm.org/D53977 llvm-svn: 346133
* [AMDGPU] Fix the new atomic optimizer in pixel shaders.Neil Henning2018-11-051-2/+39
| | | | | | | | | | | | | | | | | The new atomic optimizer I previously added in D51969 did not work correctly when a pixel shader was using derivatives, and had helper lanes active. To fix this we add an llvm.amdgcn.ps.live call that guards a branch around the entire atomic operation - ensuring that all helper lanes are inactive within the wavefront when we compute our atomic results. I've added a test case that can cause derivatives, and exposes the problem. Differential Revision: https://reviews.llvm.org/D53930 llvm-svn: 346128
* [ARM] Turn assert into condition in ARMCGPSam Parker2018-11-051-3/+3
| | | | | | | | | Turn the assert in PrepareConstants into a conditon so that we can handle mul instructions with negative immediates. Differential Revision: https://reviews.llvm.org/D54094 llvm-svn: 346126
* [ARM][ARMCGP] Remove unecessary zexts and truncsSam Parker2018-11-051-33/+68
| | | | | | | | | | | | | | | | | | | r345840 slightly changed the way promotion happens which could result in zext and truncs having the same source and destination types. This fixes that issue. We can now also remove the zext and trunc in the following case: (zext (trunc (promoted op)), i32) This means that we can no longer treat a value, that is only used by a sink, to be safe to promote. I've also added in some extra asserts and replaced a cast for a dyn_cast. Differential Revision: https://reviews.llvm.org/D54032 llvm-svn: 346125
* [AVR] Fix a backend bug that left extraneous operands after expansionDylan McKay2018-11-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug in the AVR FRMIDX expansion logic. The expansion would leave a leftover operand from the original FRMIDX, but now attached to a MOVWRdRr instruction. The MOVWRdRr instruction did not expect this operand and so LLVM rejected the machine instruction. This would trigger an assertion: Assertion failed: ((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isMetaDataOp) && "Trying to add an operand to a machine instr that is already done!"), function addOperand, file llvm/lib/CodeGen/MachineInstr.cpp Tim fixed this so that now the FRMIDX is expanded correctly into a well-formed MOVWRdRr. Patch by Tim Neumann llvm-svn: 346117
* [X86] Custom type legalize v2i8/v2i16/v2i32 mul to use to pmuludq.Craig Topper2018-11-051-0/+42
| | | | | | v2i8/v2i16/v2i32 are promoted to v2i64. pmuludq takes a v2i64 input and produces a v2i64 output. Since we don't about the upper bits of the type legalized multiply we can use the pmuludq to produce the multiply result for the bits we do care about. llvm-svn: 346115
* [AVR] Disallow the LDDWRdPtrQ instruction with Z as the destinationDylan McKay2018-11-052-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an AVR-specific workaround for a limitation of the register allocator that only exposes itself on targets with high register contention like AVR, which only has three pointer registers. The three pointer registers are X, Y, and Z. In most nontrivial functions, Y is reserved for the frame pointer, as per the calling convention. This leaves X and Z. Some instructions, such as LPM ("load program memory"), are only defined for the Z register. Sometimes this just leaves X. When the backend generates a LDDWRdPtrQ instruction with Z as the destination pointer, it usually trips up the register allocator with this error message: LLVM ERROR: ran out of registers during register allocation This patch is a hacky workaround. We ban the LDDWRdPtrQ instruction from ever using the Z register as an operand. This gives the register allocator a bit more space to allocate, fixing the regalloc exhaustion error. Here is a description from the patch author Peter Nimmervoll As far as I understand the problem occurs when LDDWRdPtrQ uses the ptrdispregs register class as target register. This should work, but the allocator can't deal with this for some reason. So from my testing, it seams like (and I might be totally wrong on this) the allocator reserves the Z register for the ICALL instruction and then the register class ptrdispregs only has 1 register left and we can't use Y for source and destination. Removing the Z register from DREGS fixes the problem but removing Y register does not. More information about the bug can be found on the avr-rust issue tracker at https://github.com/avr-rust/rust/issues/37. A bug has raised to track the removal of this workaround and a proper fix; PR39553 at https://bugs.llvm.org/show_bug.cgi?id=39553. Patch by Peter Nimmervoll llvm-svn: 346114
* [X86] Add vector shift by immediate to SimplifyDemandedBitsForTargetNode.Craig Topper2018-11-041-0/+42
| | | | | | | | | | | | | | Summary: This also enables some constant folding from KnownBits propagation. This helps on some cases vXi64 case in 32-bit mode where constant vectors appear as vXi32 and a bitcast. This can prevent getNode from constant folding sra/shl/srl. Reviewers: RKSimon, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54069 llvm-svn: 346102
* [SelectionDAG] Remove special methods for creating *_EXTEND_VECTOR_INREG ↵Craig Topper2018-11-042-15/+21
| | | | | | | | | | nodes. Move asserts into getNode. These methods were just wrappers around getNode with additional asserts (identical and repeated 3 times). But getNode already has a switch that can be used to hold these asserts that allows them to be shared for all 3 opcodes. This also enables checking on the places that create these nodes without using the wrappers. The rest of the patch is just changing all callers to use getNode directly. llvm-svn: 346087
* [X86] Update comment I forgot to change in r346043. NFCCraig Topper2018-11-031-2/+2
| | | | llvm-svn: 346073
* [codeview] Let the X86 backend tell us the VFRAME offset adjustmentReid Kleckner2018-11-031-9/+9
| | | | | | | | | | | Use MachineFrameInfo's OffsetAdjustment field to pass this information from the target to CodeViewDebug.cpp. The X86 backend doesn't use it for any other purpose. This fixes PR38857 in the case where there is a non-aligned quantity of CSRs and a non-aligned quantity of locals. llvm-svn: 346062
* [X86] In LowerEXTEND_VECTOR_INREG, emit a vector shuffle instead of directly ↵Craig Topper2018-11-021-1/+1
| | | | | | | | using X86ISD::UNPCKL The majority of the changes are because the rest of shuffle lowering/combining prefers to replace the undef input with the other operand. Using UNPCKL directly seemed to avoid this and just grabbed a randomish register for the undef which can create false dependencies. llvm-svn: 346050
* [WebAssembly] Parsing missing directives to produce valid .oWouter van Oortmerssen2018-11-021-32/+100
| | | | | | | | | | | | | | | | | | | | | | | Summary: The assembler was able to assemble and then dump back to .s, but was failing to parse certain directives necessary for valid .o output: - .type directives are now recognized to distinguish function symbols and others. - .size is now parsed to provide function size. - .globaltype (introduced in https://reviews.llvm.org/D54012) is now recognized to ensure symbols like __stack_pointer have a proper type set for both .s and .o output. Also added tests for the above. Reviewers: sbc100, dschuff Subscribers: jgravelle-google, aheejin, dexonsmith, kristina, llvm-commits, sunfish Differential Revision: https://reviews.llvm.org/D53842 llvm-svn: 346047
* [X86] Don't emit *_extend_vector_inreg nodes when both the input and output ↵Craig Topper2018-11-021-27/+18
| | | | | | | | | | | | | | | | types are legal with AVX1 We already have custom lowering for the AVX case in LegalizeVectorOps. So its better to keep the regular extend op around as long as possible. I had to qualify one place in DAG combine that created illegal vector extending load operations. This change by itself had no effect on any tests which is why its included here. I've made a few cleanups to the custom lowering. The sign extend code no longer creates an identity shuffle with undef elements. The zero extend code now emits a zero_extend_vector_inreg instead of an unpckl with a zero vector. For the high half of the custom lowering of zero_extend/any_extend, we're now using an unpckh with a zero vector or undef. Previously we used used a pshufd to move the upper 64-bits to the lower 64-bits and then used a zero_extend_vector_inreg. I think the zero vector should require less execution resources and be smaller code size. Differential Revision: https://reviews.llvm.org/D54024 llvm-svn: 346043
* [RISCV] Add some missing expansions for floating-point intrinsicsAlex Bradbury2018-11-021-0/+9
| | | | | | | | | | | | | | | | | | A number of intrinsics, such as llvm.sin.f32, would result in a failure to select. This patch adds expansions for the relevant selection DAG nodes, as well as exhaustive testing for all f32 and f64 intrinsics. The codegen for FMA remains a TODO item, pending support for the various RISC-V FMA instruction variants. The llvm.minimum.f32.* and llvm.maximum.* tests are commented-out, pending upstream support for target-independent expansion, as discussed in http://lists.llvm.org/pipermail/llvm-dev/2018-November/127408.html. Differential Revision: https://reviews.llvm.org/D54034 Patch by Luís Marques. llvm-svn: 346034
* [WebAssembly] Fix bugs in rethrow depth counting and InstPrinterHeejin Ahn2018-11-022-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: EH stack depth is incremented at `try` and decremented at `catch`. When there are more than two catch instructions for a try instruction, we shouldn't count non-first catches when calculating EH stack depths. This patch fixes two bugs: - CFGStackify: Exclude `catch_all` in the terminate catch pad when calculating EH pad stack, because when we have multiple catches for a try we should count only the first catch instruction when calculating EH pad stack. - InstPrinter: The initial intention was also to exclude non-first catches, but it didn't account nested try-catches, so it failed on this case: ``` try try catch end catch <-- (1) end ``` In the example, when we are at the catch (1), the last seen EH instruction is not `try` but `end_try`, violating the wrong assumption. We don't need these after we switch to the second proposal because there is gonna be only one `catch` instruction. But anyway before then these bugfixes are necessary for keep trunk in working state. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53819 llvm-svn: 346029
* ARMExpandPseudoInsts: Fix CMP_SWAP expansion adding a kill flag to a defMatthias Braun2018-11-021-4/+5
| | | | llvm-svn: 346026
* [SystemZ::TTI] Improve cost handling of uint/sint to fp conversions.Jonas Paulsson2018-11-021-4/+6
| | | | | | | | | | | | Let i8/i16 uint/sint to fp conversions cost 1 if operand is a load. Since the load already does the extension, there is no extra cost (previously returned 2). Review: Ulrich Weigand https://reviews.llvm.org/D54028 llvm-svn: 346009
* Fixed inclusion of M_PI fow MinGW-w64Sylvestre Ledru2018-11-021-1/+1
| | | | | | Patch by KOLANICH llvm-svn: 346000
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