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* Add checkevent intrinsic to check if any resources owned by the current threadRichard Osborne2011-03-162-55/+134
| | | | | | can event. llvm-svn: 127741
* There were two issues fixed:Johnny Chen2011-03-151-12/+5
| | | | | | | | | | | | | | | | 1. The ARM Darwin *r9 call instructions were pseudo-ized recently. Modify the ARMDisassemblerCore.cpp file to accomodate the change. 2. The disassembler was unnecessarily adding 8 to the sign-extended imm24: imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate) // Encoding A1 It has no business doing such. Removed the offending logic. Add test cases to arm-tests.txt. llvm-svn: 127707
* The VTBL (and VTBX) instructions are rather permissive concerning the masks theyBill Wendling2011-03-151-0/+8
| | | | | | | accept. If a value in the mask is out of range, it uses the value 0, for VTBL, or leaves the value unchanged, for VTBX. llvm-svn: 127700
* Some minor cleanups based on feedback.Bill Wendling2011-03-152-8/+4
| | | | llvm-svn: 127694
* Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587Evan Cheng2011-03-151-9/+3
| | | | llvm-svn: 127683
* Don't indent cases in a switch, no functionality change.Richard Osborne2011-03-151-50/+50
| | | | llvm-svn: 127681
* On the XCore the scavenging slot should be closest to the SP.Richard Osborne2011-03-152-0/+7
| | | | llvm-svn: 127680
* Add XCore intrinsics for getps, setps, setsr and clrsr.Richard Osborne2011-03-151-3/+25
| | | | llvm-svn: 127678
* PTX: Set PTX 2.0 as the minimum supported versionJustin Holewinski2011-03-155-42/+80
| | | | | | | | - Remove PTX 1.4 code generation - Change type of intrinsics to .v4.i32 instead of .v4.i16 - Add and/or/xor integer instructions llvm-svn: 127677
* Avoid a compiler warning about reg possibly being used uninitializedDuncan Sands2011-03-151-4/+2
| | | | | | when building with assertions disabled. llvm-svn: 127675
* Enabled disassembler support for AVX instructionsSean Callanan2011-03-152-150/+152
| | | | | | | | in the instruction tables and fixed a few bugs that were causing decode conflicts. Rudimentary tests are coming up in the next patch. llvm-svn: 127646
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-154-42/+319
| | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. llvm-svn: 127644
* Fixed an ARM disassembler bug where it does not handle STRi12 correctly ↵Johnny Chen2011-03-151-6/+9
| | | | | | | | | | because an extra register operand was erroneously added. Remove an incorrect assert which triggers the bug. rdar://problem/9131529 llvm-svn: 127642
* Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.Jim Grosbach2011-03-153-31/+71
| | | | | | | Also more cleanly separate the ARM vs. Thumb functionality. Previously, the encoding would be incorrect for some Thumb instructions (the indirect calls). llvm-svn: 127637
* Generate a VTBL instruction instead of a series of loads and stores when weBill Wendling2011-03-143-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better than this: _shuf: @ BB#0: @ %entry push {r4, r7, lr} add r7, sp, #4 sub sp, #12 mov r4, sp bic r4, r4, #7 mov sp, r4 mov r2, sp vmov d16, r0, r1 orr r0, r2, #6 orr r3, r2, #7 vst1.8 {d16[0]}, [r3] vst1.8 {d16[5]}, [r0] subs r4, r7, #4 orr r0, r2, #5 vst1.8 {d16[4]}, [r0] orr r0, r2, #4 vst1.8 {d16[4]}, [r0] orr r0, r2, #3 vst1.8 {d16[0]}, [r0] orr r0, r2, #2 vst1.8 {d16[2]}, [r0] orr r0, r2, #1 vst1.8 {d16[1]}, [r0] vst1.8 {d16[3]}, [r2] vldr.64 d16, [sp] vmov r0, r1, d16 mov sp, r4 pop {r4, r7, pc} The "illegal" testcase in vext.ll is no longer illegal. <rdar://problem/9078775> llvm-svn: 127630
* Remove some dead patterns.Jim Grosbach2011-03-144-56/+0
| | | | llvm-svn: 127601
* Indentation.Evan Cheng2011-03-141-1/+1
| | | | llvm-svn: 127595
* PTX: Emit global arrays with proper sizesJustin Holewinski2011-03-141-5/+34
| | | | | | | - Emit all arrays as type .b8 and proper sizes in bytes to conform to the output of nvcc llvm-svn: 127584
* PTX: Add support for sqrt/sin/cos intrinsicsJustin Holewinski2011-03-141-0/+33
| | | | llvm-svn: 127578
* ptx: add set.p instruction and related changes to predicate executionChe-Liang Chiou2011-03-144-17/+59
| | | | llvm-svn: 127577
* ptx: add basic support of predicate executionChe-Liang Chiou2011-03-134-59/+177
| | | | llvm-svn: 127569
* Sometimes isPredicable lies to us and tells us we don't need the operands.Eric Christopher2011-03-121-6/+25
| | | | | | | | | Go ahead and add them on when we might want to use them and let later passes remove them. Fixes rdar://9118569 llvm-svn: 127518
* Add FIXME.Jim Grosbach2011-03-121-0/+3
| | | | llvm-svn: 127516
* Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the sameJim Grosbach2011-03-122-27/+33
| | | | | | | | actual instruction as the non-Darwin defs, but have different call-clobber semantics and so need separate patterns. They don't need to duplicate the encoding information, however. llvm-svn: 127515
* Add a FIXME.Jim Grosbach2011-03-111-0/+2
| | | | llvm-svn: 127511
* Pseudo-ize the ARM 'B' instruction.Jim Grosbach2011-03-112-7/+14
| | | | llvm-svn: 127510
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-111-1/+1
| | | | llvm-svn: 127509
* Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach2011-03-112-6/+17
| | | | llvm-svn: 127506
* 80 columnsJim Grosbach2011-03-111-1/+2
| | | | llvm-svn: 127505
* Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-Jim Grosbach2011-03-112-10/+14
| | | | | | effect that we get proper instruction printing using the "pop" mnemonic for it. llvm-svn: 127502
* ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach2011-03-111-8/+2
| | | | | | as for VDUP32d and VDUP32q, respectively. llvm-svn: 127489
* ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach2011-03-112-8/+9
| | | | | | and VDUPLN32d, respectively. llvm-svn: 127486
* ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach2011-03-111-2/+2
| | | | | | as for VREV64d32 and VREV64q32, respectively. llvm-svn: 127485
* This FIXME has been fixed.Jim Grosbach2011-03-111-3/+0
| | | | llvm-svn: 127483
* Properly pseudo-ize ARM MVNCCi.Jim Grosbach2011-03-112-12/+15
| | | | llvm-svn: 127482
* Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).Jim Grosbach2011-03-111-3/+3
| | | | llvm-svn: 127469
* silence a conditional assignment -Wuninitialized warning.Chris Lattner2011-03-111-1/+1
| | | | llvm-svn: 127453
* Properly pseudo-ize ARM MOVCCi and MOVCCi16.Jim Grosbach2011-03-112-26/+30
| | | | llvm-svn: 127442
* Change the x86 32-bit scheduler to register pressure and fix up theEric Christopher2011-03-111-1/+7
| | | | | | | | corresponding testcases back to the previous versions. Fixes some performance regressions only seen on 32-bit. llvm-svn: 127441
* Properly pseudo-ize MOVCCr and MOVCCs.Jim Grosbach2011-03-102-26/+36
| | | | llvm-svn: 127434
* DMB can just be a pat referencing MCR.Jim Grosbach2011-03-101-7/+6
| | | | llvm-svn: 127423
* Reorganize a bit. No functional change, just moving patterns up.Jim Grosbach2011-03-101-232/+233
| | | | llvm-svn: 127422
* Pseudo-instructions are codegenonly by definition.Jim Grosbach2011-03-101-0/+1
| | | | llvm-svn: 127420
* PTX: Add preliminary support for floating-point divide and multiply-and-addJustin Holewinski2011-03-102-5/+104
| | | | llvm-svn: 127410
* ptx: add the rest of special registers of ISA version 2.0Che-Liang Chiou2011-03-101-7/+43
| | | | llvm-svn: 127397
* Revert 127359; it broke lencod.Stuart Hastings2011-03-101-1/+1
| | | | llvm-svn: 127382
* Re-commit 127368 and 127371. They are exonerated.Evan Cheng2011-03-101-1/+1
| | | | llvm-svn: 127380
* Revert 127368 and 127371 for now.Evan Cheng2011-03-091-1/+1
| | | | llvm-svn: 127376
* Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng2011-03-091-1/+1
| | | | | | | | | | | | | flexible. If it returns a register class that's different from the input, then that's the register class used for cross-register class copies. If it returns a register class that's the same as the input, then no cross- register class copies are needed (normal copies would do). If it returns null, then it's not at all possible to copy registers of the specified register class. llvm-svn: 127368
* Fix a pasto that broke all x86_64-elf targets.Benjamin Kramer2011-03-091-1/+1
| | | | llvm-svn: 127365
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