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* [X86] Change RDRAND to use PS instead of TB.Craig Topper2017-10-231-3/+3
| | | | | | Should be no functional change for now. A future disassembler change will prevent disassembling with 0xf2/0xf3. llvm-svn: 316339
* [X86] Change XRSTOR to use PS instead of TB to match XSAVE.Craig Topper2017-10-231-2/+2
| | | | | | I don't think this changes anything functionally yet, but I plan to fix the disassembler to use this to disable matching certain instructions with 0xf3/0xf2/0x66 prefixes. llvm-svn: 316337
* [X86][SSE] Remove AssertZext stage from PEXTRW/PEXTRB lowering. NFCI.Simon Pilgrim2017-10-233-33/+30
| | | | | | | | Remove AssertZext and instead add PEXTRW/PEXTRB support to computeKnownBitsForTargetNode to simplify instruction selection. Differential Revision: https://reviews.llvm.org/D39169 llvm-svn: 316336
* Update DPPD/DPPS instruction scheduling on btver2.Andrew V. Tischenko2017-10-231-0/+46
| | | | | | Differential Revision: https://reviews.llvm.org/D39046 llvm-svn: 316334
* [X86] Add PTWRITE instruction for assembler and disassembler.Craig Topper2017-10-231-2/+14
| | | | llvm-svn: 316333
* [X86] Add RDPID instruction for assembler and disassembler.Craig Topper2017-10-232-3/+12
| | | | llvm-svn: 316332
* Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue ↵Andrew V. Tischenko2017-10-231-2/+2
| | | | | | | | was in illegal segment register index. Differential Revision: https://reviews.llvm.org/D38786 llvm-svn: 316319
* Fix a -Wpedantic warning.Haojian Wu2017-10-231-1/+1
| | | | llvm-svn: 316315
* [ARM] Allow unrolling of multi-block loops.Sam Parker2017-10-231-16/+35
| | | | | | | | | | | Before, loop unrolling was only enabled for loops with a single block. This restriction has been removed and replaced by: - allow a maximum of two exiting blocks, - a four basic block limit for cores with a branch predictor. Differential Revision: https://reviews.llvm.org/D38952 llvm-svn: 316313
* [X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper2017-10-234-0/+11
| | | | | | Fixes PR31955. llvm-svn: 316308
* [X86] Add missing override. NFC.Benjamin Kramer2017-10-221-3/+1
| | | | llvm-svn: 316299
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-10-221-2/+2
| | | | llvm-svn: 316296
* Add logic to greedy reg alloc to avoid bad eviction chainsMarina Yatsina2017-10-221-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes bugzilla 26810 https://bugs.llvm.org/show_bug.cgi?id=26810 This is intended to prevent sequences like: movl %ebp, 8(%esp) # 4-byte Spill movl %ecx, %ebp movl %ebx, %ecx movl %edi, %ebx movl %edx, %edi cltd idivl %esi movl %edi, %edx movl %ebx, %edi movl %ecx, %ebx movl %ebp, %ecx movl 16(%esp), %ebp # 4 - byte Reload Such sequences are created in 2 scenarios: Scenario #1: vreg0 is evicted from physreg0 by vreg1 Evictee vreg0 is intended for region splitting with split candidate physreg0 (the reg vreg0 was evicted from) Region splitting creates a local interval because of interference with the evictor vreg1 (normally region spliiting creates 2 interval, the "by reg" and "by stack" intervals. Local interval created when interference occurs.) one of the split intervals ends up evicting vreg2 from physreg1 Evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills Scenario #2 vreg0 is evicted from physreg0 by vreg1 vreg2 is evicted from physreg2 by vreg3 etc Evictee vreg0 is intended for region splitting with split candidate physreg1 Region splitting creates a local interval because of interference with the evictor vreg1 one of the split intervals ends up evicting back original evictor vreg1 from physreg0 (the reg vreg0 was evicted from) Another evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills As compile time was a concern, I've added a flag to control weather we do cost calculations for local intervals we expect to be created (it's on by default for X86 target, off for the rest). Differential Revision: https://reviews.llvm.org/D35816 Change-Id: Id9411ff7bbb845463d289ba2ae97737a1ee7cc39 llvm-svn: 316295
* [ARM] Dynamic stack alignment for 16-bit ThumbMomchil Velikov2017-10-223-16/+38
| | | | | | | | | | | This patch implements dynamic stack (re-)alignment for 16-bit Thumb. When targeting processors, which support only the 16-bit Thumb instruction set the compiler ignores the alignment attributes of automatic variables and may silently generate incorrect code. Differential revision: https://reviews.llvm.org/D38143 llvm-svn: 316289
* [X86] Add a pass to convert instruction chains between domains.Guy Blank2017-10-224-0/+764
| | | | | | | | | | | | | | | | | The pass scans the function to find instruction chains that define registers in the same domain (closures). It then calculates the cost of converting the closure to another domain. If found profitable, the instructions are converted to instructions in the other domain and the register classes are changed accordingly. This commit adds the pass infrastructure and a simple conversion from the GPR domain to the Mask domain. Differential Revision: https://reviews.llvm.org/D37251 Change-Id: Ic2cf1d76598110401168326d411128ae2580a604 llvm-svn: 316288
* [X86] Add VEX_WIG to applicable AVX512 instructions.Craig Topper2017-10-221-41/+43
| | | | | | This should be NFC. Will be used in future patches to fix disassembler bugs. llvm-svn: 316284
* [X86] Add VEX_WIG to VROUNDSSrr/VROUNDSSrm/VROUNDSDrr/VROUNDSDrmCraig Topper2017-10-221-1/+1
| | | | llvm-svn: 316283
* [X86] Don't allow gather/scatter to disassembler if memory operand does not ↵Craig Topper2017-10-221-0/+4
| | | | | | | | use a SIB byte. Fixes PR34998. llvm-svn: 316282
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-10-211-4/+4
| | | | llvm-svn: 316277
* Reverting r316270 due to failing build bots.Aaron Ballman2017-10-211-8/+6
| | | | | | | http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/12899 http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/7951 llvm-svn: 316276
* [X86][SSE] Add extractps/pextrd equivalence to domain tablesSimon Pilgrim2017-10-211-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D39135 llvm-svn: 316274
* [X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper2017-10-214-118/+44
| | | | | | | | | | | | the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
* Fix MSVC 'result of 32-bit shift implicitly converted to 64 bits' warning. NFCI.Simon Pilgrim2017-10-211-2/+2
| | | | llvm-svn: 316271
* [PPC CodeGen] Fix the bitreverse.i64 intrinsic.Fangrui Song2017-10-211-6/+8
| | | | | | | | | | Summary: The two 32-bit words were swapped. Subscribers: nemanjai, kbarton Differential Revision: https://reviews.llvm.org/D38705 llvm-svn: 316270
* [X86] Do not generate __multi3 for mul i128 on X86Craig Topper2017-10-211-0/+1
| | | | | | | | | | | | | | | | Summary: __multi3 is not available on x86 (32-bit). Setting lib call name for MULI_128 to nullptr forces DAGTypeLegalizer::ExpandIntRes_MUL to generate instructions for 128-bit multiply instead of a call to an undefined function. This fixes PR20871 though it may be worth looking at why licm and indvars combine to generate 65-bit multiplies in that test. Patch by Riyaz V Puthiyapurayil Reviewers: craig.topper, schweitz Reviewed By: craig.topper, schweitz Subscribers: RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D38668 llvm-svn: 316254
* [Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek2017-10-201-1/+1
| | | | llvm-svn: 316243
* [WebAssembly] MC: Fix crash when -g specified.Sam Clegg2017-10-201-4/+4
| | | | | | | | | At this point we don't output any debug sections or thier relocations. Differential Revision: https://reviews.llvm.org/D39076 llvm-svn: 316240
* [globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders2017-10-201-14/+14
| | | | | | | ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. llvm-svn: 316237
* [Hexagon] Report error instead of crashing on wrong inline-asm constraintsKrzysztof Parzyszek2017-10-201-13/+14
| | | | llvm-svn: 316236
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-2010-2623/+2244
| | | | llvm-svn: 316228
* [X86][SSE] getTargetShuffleMask - check shuffle input value types. NFCI.Simon Pilgrim2017-10-201-0/+46
| | | | | | To help identify shuffle combine issues llvm-svn: 316222
* Make x86 __ehhandler comdat if parent function isDave Lee2017-10-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change comes from using lld for i686-windows-msvc. Before this change, lld emits an error of: error: relocation against symbol in discarded section: .xdata It's possible that this could be addressed in lld, but I think this change is reasonable on its own. At a high level, this is being generated: A (.text comdat) -> B (.text) -> C (.xdata comdat) Where A is a C++ inline function, which references B, an exception handler thunk, which references C, the exception handling info. With this structure, lld will error when applying relocations to B if the C it references has been discarded (some other C has been selected). This change checks if A is comdat, and if so places the exception registration thunk (B) in the comdata group of A (and B). It appears that MSVC makes the __ehhandler function comdat. Is it possible that duplicate thunks are being emitted into the final binary with other linkers, or are they stripping the unused thunks? Reviewers: rnk, majnemer, compnerd, smeenai Reviewed By: rnk, compnerd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38940 llvm-svn: 316219
* [Hexagon] Allow redefinition with immediates for hw loop conversionKrzysztof Parzyszek2017-10-202-7/+13
| | | | | | | | | | | Normally, if the registers holding the induction variable's bounds are redefined inside of the loop's body, the loop cannot be converted to a hardware loop. However, if the redefining instruction is actually loading an immediate value into the register, this conversion is both possible and legal (since the immediate itself will be used in the loop setup in the preheader). llvm-svn: 316218
* Revert "[mips] Reordering callseq* nodes to be linear"Aleksandar Beserminji2017-10-202-27/+26
| | | | | | | This reverts commit r314507, because the original patch is causing test failures. llvm-svn: 316215
* [ARM] Use post-RA MI scheduler when +use-misched is setEugene Leviant2017-10-201-1/+8
| | | | | | Differential revision: https://reviews.llvm.org/D39100 llvm-svn: 316214
* Disabling the transformation introduced in r315888Nemanja Ivanovic2017-10-201-2/+2
| | | | | | | The commit at https://reviews.llvm.org/rL315888 is causing some failures with internal testing. Disabling this code until we can resolve the issues. llvm-svn: 316199
* [RISCV] Add missing hunk from r316188Alex Bradbury2017-10-191-1/+3
| | | | | | r316188 didn't set guessInstructionProperties=1 as it should have done. llvm-svn: 316189
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-1922-11/+938
| | | | | | | | | | | | | This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
* [X86] Remove LowerEXTRACT_SUBVECTOR handler. All EXTRACT_SUBVECTORs are ↵Craig Topper2017-10-191-26/+0
| | | | | | marked as legal. llvm-svn: 316182
* The cost of splitting a large vector instruction is not being taken into ↵Graham Yiu2017-10-192-0/+13
| | | | | | | | | | account by the getUserCost function. This was leading to some loops being over unrolled. The cost of a vector instruction is now being multiplied by the cost of the type legalization. This will return a more accurate cost. Committing on behalf on Brad Nemanich (brad.nemanich@ibm.com) Differential Revision: https://reviews.llvm.org/D38961 llvm-svn: 316174
* [Hexagon] Fix store conversion from rr to io in optimize addressing modesKrzysztof Parzyszek2017-10-191-6/+5
| | | | llvm-svn: 316170
* [RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expectedAlex Bradbury2017-10-191-0/+10
| | | | | | | This is necessary to avoid an assertion in the included test case and similar assembler inputs. llvm-svn: 316168
* [RISCV][NFC] Drop unused parameter from createImm helper in RISCVAsmParserAlex Bradbury2017-10-191-4/+3
| | | | llvm-svn: 316167
* [X86] Replace custom scalar integer absolute matching with ISD::ABS lowering.Simon Pilgrim2017-10-191-36/+21
| | | | | | | | | | | | x86 has its own copy of integer absolute pattern matching to combine directly to a SUB+CMOV. This patch removes the x86 combine and adds custom lowering support for ISD::ABS instead, allowing us to use the DAGCombiner version. Additional test cases are already covered by iabs.ll (rL315706 and rL315711). Differential Revision: https://reviews.llvm.org/D38895 llvm-svn: 316162
* [RISCV] Prepare for the use of variable-sized register classesAlex Bradbury2017-10-198-220/+276
| | | | | | | | | | While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159
* [Hexagon] New HVX target features.Sumanth Gundapaneni2017-10-187-86/+111
| | | | | | | | | | | | | | | | | | | | | | This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
* [Hexagon] Update Hexagon ArchEnum and sync some downstream changes(NFC)Sumanth Gundapaneni2017-10-186-68/+76
| | | | | | Differential Revision: https://reviews.llvm.org/D38850 llvm-svn: 316099
* [Hexagon] Mark vector loads as predicable, update instruction mappingsKrzysztof Parzyszek2017-10-182-56/+154
| | | | | | | | All loads of form V6_vL32b_{,cur,nt,tmp,nt_cur,nt_tmp}_{ai,pi,ppu} are predicable on v62 (but not on v60). Mark them all as predicable in the instruction definitions, and handle the v60 case in HII::isPredicable. llvm-svn: 316098
* AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistencyKonstantin Zhuravlyov2017-10-181-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D38957 llvm-svn: 316097
* [RISCV] Bugfix createRISCVELFObjectWriterAlex Bradbury2017-10-181-1/+1
| | | | | | | r315275 set the IsLittleEndian parameter incorrectly. This patch corrects this, and adds a test to ensure such mistakes will be caught in the future. llvm-svn: 316091
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