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* Move PPCInstrInfo off of the target machine and onto the subtarget.Eric Christopher2014-06-124-7/+11
| | | | llvm-svn: 210839
* Remove TargetMachine from PPCInstrInfo and all dependencies andEric Christopher2014-06-125-27/+29
| | | | | | replace with the current subtarget. llvm-svn: 210836
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-128-240/+32
| | | | | | | | | Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
* Move DataLayout from the PPCTargetMachine to the subtarget.Eric Christopher2014-06-124-40/+46
| | | | llvm-svn: 210824
* Move PPCFrameLowering into PPCSubtarget from PPCTargetMachine. UseEric Christopher2014-06-126-196/+211
| | | | | | | | the initializeSubtargetDependencies code to obtain an initialized subtarget and migrate a couple of subtarget using functions to the .cpp file to avoid circular includes. llvm-svn: 210822
* [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.Juergen Ributzka2014-06-121-20/+41
| | | | | | | Recommit with fixed argument attribute checking code, which is required to bail out of all the cases we don't handle yet. llvm-svn: 210815
* CodeGen: enable mov.w/mov.t pairs with minsize for WoASaleem Abdulrasool2014-06-121-1/+6
| | | | | | | | | Windows on ARM uses COFF/PE which is intrinsically position independent. For the case of 32-bit immediates, use a pair-wise relocation as otherwise we may exceed the range of operators. This fixes a code generation crash when using -Oz when targeting Windows on ARM. llvm-svn: 210814
* Revert "[FastIsel][X86] Add support for lowering the first 8 floating-point ↵Juergen Ributzka2014-06-121-36/+19
| | | | | | | | arguments." Reverting it because it breaks several tests. llvm-svn: 210810
* X86: stifle GCC warningSaleem Abdulrasool2014-06-121-1/+3
| | | | | | | | | | lib/Target/X86/X86TargetTransformInfo.cpp: In member function ‘virtual unsigned int {anonymous}::X86TTI::getIntImmCost(unsigned int, unsigned int, const llvm::APInt&, llvm::Type*) const’: lib/Target/X86/X86TargetTransformInfo.cpp:920:60: warning: enumeral and non-enumeral type in conditional expression [enabled by default] This seems like an unhelpful warning, but there doesnt seem to be a controlling flag, so add an explicit cast to silence the warning. llvm-svn: 210806
* Disable the load/store optimization pass for Thumb-1.James Molloy2014-06-121-3/+7
| | | | | | | | Moritz's changes have improved codegen a lot, but further testing showed significant correctness problems. Disable by default until these have been worked out. Patch by Moritz Roth! llvm-svn: 210789
* [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-125-8/+21
| | | | | | | | | | | | | | | | | | | | Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
* [mips][mips64r6] bc2[ft] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-121-2/+0
| | | | | | | | | | | | | | | | Summary: These instructions are not implemented for any MIPS ISA so we only need testcases. Depends on D4110 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4111 llvm-svn: 210786
* [mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-124-24/+24
| | | | | | | | | | | | | | | | | Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
* [mips][mips64r6] prefx is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-121-1/+0
| | | | | | | | | | | | Summary: We haven't implemented this instruction so we only add a test case. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D4004 llvm-svn: 210779
* [mips][mips64r6] 80 col corrections that should have been in r210777.Daniel Sanders2014-06-121-10/+20
| | | | llvm-svn: 210778
* [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available ↵Daniel Sanders2014-06-1211-89/+426
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
* [mips][mips64r6] jalx is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-122-4/+5
| | | | | | | | | | | | Summary: Depends on D3957 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3958 llvm-svn: 210775
* [mips][mips64r6] Add R_MIPS_PC19_S2Zoran Jovanovic2014-06-125-5/+31
| | | | | | Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
* [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-06-123-17/+46
| | | | | | | | | | | | | | | | | | | | | | FP64 Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 llvm-svn: 210771
* [mips][mips64r6] Add bgec and bgeuc instructionsZoran Jovanovic2014-06-122-6/+68
| | | | | | Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
* [X86] Teach how to dump the name of target node RDTSCP_DAG.Andrea Di Biagio2014-06-121-0/+1
| | | | | | | | | When I originally added node RDTSCP_DAG (r207127) I forgot to add a string name for it in method 'getTargetNodeName'. No functional change intended. llvm-svn: 210769
* [mips][mips64r6] madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not ↵Daniel Sanders2014-06-123-13/+15
| | | | | | | | | | | | | | | | | | | | available on MIPS32r6/MIPS64r6 Summary: This patch updates both the assembler and the code generator. MIPS32r6/MIPS64r6 replaces them with maddf.[ds] and msubf.[ds] which are fused multiply-add/sub operations. We don't emit these yet, this patch only prevents the removed instructions from being emitted. Depends on D3955 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3956 llvm-svn: 210763
* [mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-123-11/+20
| | | | | | | | | | | | | | | | Summary: This patch disables madd/maddu/msub/msubu in both the assembler and code generator. Depends on D3896 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3955 llvm-svn: 210762
* [X86] Teach how to combine AVX and AVX2 horizontal binop on packed 256-bit ↵Andrea Di Biagio2014-06-121-9/+103
| | | | | | | | | | | vectors. This patch adds target combine rules to match: - [AVX] Horizontal add/sub of packed single/double precision floating point values from 256-bit vectors; - [AVX2] Horizontal add/sub of packed integer values from 256-bit vectors. llvm-svn: 210761
* [mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ↵Daniel Sanders2014-06-127-60/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
* R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*Matt Arsenault2014-06-122-41/+29
| | | | | | | There is not such thing as a 0-data ds instruction, and the data operand needs to be a vgpr set to something meaningful. llvm-svn: 210756
* [FastISel][X86] Add support for the sqrt intrinsic.Juergen Ributzka2014-06-111-0/+52
| | | | llvm-svn: 210720
* [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.Juergen Ributzka2014-06-111-19/+36
| | | | llvm-svn: 210719
* [FastISel][X86] Add support for the frameaddress intrinsic.Juergen Ributzka2014-06-111-0/+52
| | | | llvm-svn: 210709
* [AArch64] Basic Sched Model for Cortex-A57.Chad Rosier2014-06-113-1/+818
| | | | | | | Patch by Dave Estes<cestes@codeaurora.org> Differential Revision: http://reviews.llvm.org/D4008 llvm-svn: 210705
* R600: Set correct InstrItinClass for instructions using *Helper classesTom Stellard2014-06-111-3/+3
| | | | | | | | | We weren't doing this before, so all instruction using the *Helper classes were considered for any ALU slot. This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test. llvm-svn: 210703
* R600: BCNT_INT is a vector only instructionTom Stellard2014-06-111-1/+1
| | | | llvm-svn: 210702
* ARM: honor hex immediate formatting for ldr/str i12 offsets.Jim Grosbach2014-06-111-2/+2
| | | | | | | | | | | | | | | | | Previously we would always print the offset as decimal, regardless of the formatting requested. Now we use the formatImm() helper so the value is printed as the client (LLDB in the motivating example) requested. Before: ldr.w r8, [sp, #180] @ always After: ldr.w r8, [sp, #0xb4] @ when printing hex immediates ldr.w r8, [sp, #0180] @ when printing decimal immediates rdar://17237103 llvm-svn: 210701
* R600/SI: Fix bitcast between v2i32 and f64Matt Arsenault2014-06-111-0/+2
| | | | | | | | | | This is the same problem fixed in r210664 for more types. The test passes without this fix. For some reason I'm only hitting this when creating selects lowered to v2i32 selects. llvm-svn: 210692
* R600/SI: Update place using old subtarget predicateMatt Arsenault2014-06-111-2/+2
| | | | llvm-svn: 210683
* R600/SI: Add common 64-bit LDS atomicsMatt Arsenault2014-06-113-17/+43
| | | | llvm-svn: 210680
* R600/SI: Add instruction definitions for 64-bit LDS atomicsMatt Arsenault2014-06-111-0/+47
| | | | llvm-svn: 210679
* R600/SI: Add 32-bit LDS atomic cmpxchgMatt Arsenault2014-06-112-0/+24
| | | | llvm-svn: 210678
* R600/SI: Use LDS atomic inc / decMatt Arsenault2014-06-111-0/+16
| | | | llvm-svn: 210677
* R600/SI: Add other LDS atomic operationsMatt Arsenault2014-06-111-3/+12
| | | | llvm-svn: 210676
* R600/SI: Add instruction definitions for more LDS opsMatt Arsenault2014-06-112-0/+104
| | | | llvm-svn: 210675
* R600/SI: Fix backwards names for local atomic instructions.Matt Arsenault2014-06-111-4/+4
| | | | | | | The manual lists them as *_RTN_U32, not *_U32_RTN, which is more consistent with how every other sized instruction is named. llvm-svn: 210674
* R600/SI: Refactor local atomics.Matt Arsenault2014-06-112-11/+30
| | | | | | | Use patterns that will also match the immediate offset to match the normal read / writes. llvm-svn: 210673
* R600/SI: Use v_cvt_f32_ubyte* instructionsMatt Arsenault2014-06-117-5/+170
| | | | | | | This eliminates extra extract instructions when loading an i8 vector to a float vector. llvm-svn: 210666
* R600/SI: Fix selection failure on scalar_to_vectorMatt Arsenault2014-06-112-6/+23
| | | | | | | | | | | There seem to be only 2 places that produce these, and it's kind of tricky to hit them. Also fixes failure to bitcast between i64 and v2f32, although this for some reason wasn't actually broken in the simple bitcast testcase, but did in the scalar_to_vector one. llvm-svn: 210664
* X86: add stringy name for X86ISD::LCMPXCHG16_DAGTim Northover2014-06-111-0/+1
| | | | | | | I don't know what "target specific node #383" is, and I don't want to have to. llvm-svn: 210663
* [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register ↵Matheus Almeida2014-06-115-1/+121
| | | | | | | | | | | | | | with Hazard Barrier). Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4019 llvm-svn: 210654
* Add AVX512 masked leadz instrinsic support.Cameron McInally2014-06-111-0/+22
| | | | llvm-svn: 210652
* [X86] Refactor the logic to select horizontal adds/subs to a helper function.Andrea Di Biagio2014-06-111-90/+118
| | | | | | | | | | | | | | | This patch moves part of the logic implemented by the target specific combine rules added at r210477 to a separate helper function. This should make easier to add more rules for matching AVX/AVX2 horizontal adds/subs. This patch also fixes a problem caused by a wrong check performed on indices of extract_vector_elt dag nodes in input to the scalar adds/subs. New tests have been added to verify that we correctly check indices of extract_vector_elt dag nodes when selecting a horizontal operation. llvm-svn: 210644
* Try to fix the msvc build.Rafael Espindola2014-06-111-1/+2
| | | | llvm-svn: 210636
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