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* Bail from FastISel when we encounter a volatile memset intrinsic. Patch by IvanNick Lewycky2011-08-021-0/+3
| | | | | | Krasin! llvm-svn: 136663
* Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.Jim Grosbach2011-08-012-4/+6
| | | | llvm-svn: 136656
* Fix comments.Jim Grosbach2011-08-011-2/+2
| | | | llvm-svn: 136655
* Add v4f64 -> v2f32 fp_round support. Also add a testcase to exerciseBruno Cardoso Lopes2011-08-012-0/+7
| | | | | | | the legalizer. This commit together with the two previous ones fixes PR10495. llvm-svn: 136654
* Teach PreprocessISelDAG to be aware of vector types and to not process them.Bruno Cardoso Lopes2011-08-013-6/+11
| | | | llvm-svn: 136653
* Lower CONCAT_VECTORS to use two VINSERTF128 instructions instead ofBruno Cardoso Lopes2011-08-011-5/+48
| | | | | | using a stack store. llvm-svn: 136652
* Actually finish switching to the new system for Target sublibraryChandler Carruth2011-08-019-9/+9
| | | | | | | | | | | TableGen deps introduced in r136023. This completes the fixing that dgregor started in r136621. Sorry for missing these the first time around. This should fix some of the random race-condition failures people are still seeing with CMake. llvm-svn: 136643
* Since vectors with all ones can't be created with a 256-bit instruction,Bruno Cardoso Lopes2011-08-011-11/+13
| | | | | | | | avoid returning early for v8i32 types, which would only be valid for vector with all zeros. Also split the handling of zeros and ones into separate checking logic since they are handled differently. This fixes PR10547 llvm-svn: 136642
* Set endianess and pointer size for PPC Linux. Bug noticed by Roman Divacky.Evan Cheng2011-08-011-0/+4
| | | | llvm-svn: 136639
* Fix crash with varargs function with no named parameters.Richard Osborne2011-08-011-2/+2
| | | | llvm-svn: 136623
* Update CMake target names for tablegen-generated data in the X86 and ARM ↵Douglas Gregor2011-08-013-3/+3
| | | | | | targets. This should fix the CMake build with MSVC. llvm-svn: 136621
* Add the 'resume' instruction for the new EH rewrite.Bill Wendling2011-07-312-1/+8
| | | | | | | | | This adds the 'resume' instruction class, IR parsing, and bitcode reading and writing. The 'resume' instruction resumes propagation of an existing (in-flight) exception whose unwinding was interrupted with a 'landingpad' instruction (to be added later). llvm-svn: 136589
* Switch another of the old dependencies on implicitly produced syntheticChandler Carruth2011-07-301-1/+1
| | | | | | | rules to the new explicitly listed TableGen rules. Somehow I missed this in my original sweep. llvm-svn: 136567
* Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338,Bill Wendling2011-07-302-11/+1
| | | | | | | r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444, r136445, r136446, r136253 pending review. llvm-svn: 136556
* Add support for the 'Q' constraint.Eric Christopher2011-07-291-0/+3
| | | | | | Fixes rdar://9866494 llvm-svn: 136523
* ARM SRS instruction parsing, diassembly and encoding support.Jim Grosbach2011-07-293-25/+52
| | | | | | | | Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. llvm-svn: 136509
* ARM CPS mode immediate is 5 bits, not 4.Jim Grosbach2011-07-291-2/+2
| | | | llvm-svn: 136505
* ARM assembly parsing and encoding for RFE instruction.Jim Grosbach2011-07-293-13/+54
| | | | | | | | | | | Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. llvm-svn: 136479
* ARM SRS and RFE instructions are not code-gen only.Jim Grosbach2011-07-291-12/+7
| | | | llvm-svn: 136475
* ARM range checking for mode on CPS instruction.Jim Grosbach2011-07-291-2/+2
| | | | llvm-svn: 136473
* Update FIXME.Jim Grosbach2011-07-291-5/+2
| | | | llvm-svn: 136470
* Tweak comment.Jim Grosbach2011-07-291-1/+1
| | | | llvm-svn: 136468
* Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to beEli Friedman2011-07-291-1/+3
| | | | | | | | | working on x86 (at least for trivial testcases); other architectures will need more work so that they actually emit the appropriate instructions for orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC, Mips, and Alpha backends need such changes.) llvm-svn: 136457
* Fix two tests that I crashed in the previous commits. The mask eltsBruno Cardoso Lopes2011-07-291-5/+17
| | | | | | on the second half must be reindexed. llvm-svn: 136454
* Match VPERMIL masks more strictly and update the target specific maskBruno Cardoso Lopes2011-07-291-7/+17
| | | | | | generation to always catch the weird cases. llvm-svn: 136453
* Add DecodeShuffle shuffle support for VPERMIPD variantesBruno Cardoso Lopes2011-07-294-29/+60
| | | | llvm-svn: 136452
* Add v8i32 and v4i64 vpermil patternsBruno Cardoso Lopes2011-07-291-0/+4
| | | | llvm-svn: 136451
* Fix a bug while generating target specific VPERMIL masks: skipBruno Cardoso Lopes2011-07-291-4/+12
| | | | | | undef mask elements. This fixes PR10529. llvm-svn: 136450
* Enable usage of SSE4 extracts and inserts in their 128-bit AVX forms.Bruno Cardoso Lopes2011-07-291-39/+29
| | | | | | Also tidy up code a bit. llvm-svn: 136449
* Cleanup PALIGNR handling and remove the old palign pattern fragment.Bruno Cardoso Lopes2011-07-294-43/+23
| | | | | | | Also make PALIGNR masks to don't match 256-bits, which isn't supported It's also a step to solve PR10489 llvm-svn: 136448
* Transfer implicit operands in NEONMoveFixPass.Jakob Stoklund Olesen2011-07-291-10/+20
| | | | | | | | | Later passes /are/ using this information when running the register scavenger. This fixes the second problem in PR10520. llvm-svn: 136440
* Add -verify-arm-pseudo-expand.Jakob Stoklund Olesen2011-07-291-0/+7
| | | | | | | | | | This hidden llc option runs the machine code verifier after expanding ARM pseudo-instructions, but before if-conversion. The machine code verifier is much better at pointing out liveness errors that can trip up the register scavenger. llvm-svn: 136439
* Rewrite the CMake build to use explicit dependencies between libraries,Chandler Carruth2011-07-2957-13/+461
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | specified in the same file that the library itself is created. This is more idiomatic for CMake builds, and also allows us to correctly specify dependencies that are missed due to bugs in the GenLibDeps perl script, or change from compiler to compiler. On Linux, this returns CMake to a place where it can relably rebuild several targets of LLVM. I have tried not to change the dependencies from the ones in the current auto-generated file. The only places I've really diverged are in places where I was seeing link failures, and added a dependency. The goal of this patch is not to start changing the dependencies, merely to move them into the correct location, and an explicit form that we can control and change when necessary. This also removes a serialization point in the build because we don't have to scan all the libraries before we begin building various tools. We no longer have a step of the build that regenerates a file inside the source tree. A few other associated cleanups fall out of this. This isn't really finished yet though. After talking to dgregor he urged switching to a single CMake macro to construct libraries with both sources and dependencies in the arguments. Migrating from the two macros to that style will be a follow-up patch. Also, llvm-config is still generated with GenLibDeps.pl, which means it still has slightly buggy dependencies. The internal CMake 'llvm-config-like' macro uses the correct explicitly specified dependencies however. A future patch will switch llvm-config generation (when using CMake) to be based on these deps as well. This may well break Windows. I'm getting a machine set up now to dig into any failures there. If anyone can chime in with problems they see or ideas of how to solve them for Windows, much appreciated. llvm-svn: 136433
* PLD and PLI are not predicable in ARM mode.Jim Grosbach2011-07-281-0/+1
| | | | llvm-svn: 136427
* ARM assembly parsing and encoding for BLX (immediate).Jim Grosbach2011-07-282-2/+13
| | | | | | | | Add parsing support for BLX (immediate). Since the register operand version is predicated and the label operand version is not, we have to use some special handling to get the operand list right for matching. llvm-svn: 136406
* ARM assembly parsing and encoding for BFC and BFI.Jim Grosbach2011-07-282-0/+106
| | | | | | | Add parsing support that handles converting the lsb+width source into the odd way we represent the instruction (an inverted bitfield mask). llvm-svn: 136399
* Add fixme.Jim Grosbach2011-07-281-1/+5
| | | | llvm-svn: 136375
* Update comments.Owen Anderson2011-07-281-18/+10
| | | | llvm-svn: 136367
* Fill in some encoding information for STRD instructions.Owen Anderson2011-07-281-3/+32
| | | | llvm-svn: 136366
* Revert r136295. It broke nightly testers because some parts of codegen ↵Owen Anderson2011-07-283-41/+23
| | | | | | weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now. llvm-svn: 136362
* ARM parsing and encoding for ADR.Jim Grosbach2011-07-281-1/+1
| | | | | | The label does not have a '#' prefix. Add parsing and encoding tests. llvm-svn: 136360
* Explicitly declare a library dependency of LLVM*Desc toOscar Fuentes2011-07-286-0/+12
| | | | | | | | | | | | | | | | | | | LLVM*AsmPrinter. GenLibDeps.pl fails to detect vtable references. As this is the only referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized builds, the algorithm that creates the list of libraries to be linked into tools doesn't know about the dependency and sometimes places the libraries on the wrong order, yielding error messages like this: ../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function `llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)': ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE [llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)]+0x2a): undefined reference to `vtable for llvm::ARMInstPrinter' llvm-svn: 136328
* Invert the subvector insertion to be more likely to be taken as a COPYBruno Cardoso Lopes2011-07-281-3/+3
| | | | llvm-svn: 136324
* Add patterns to generate copies for extract_subvector instead ofBruno Cardoso Lopes2011-07-281-0/+12
| | | | | | | using vextractf128. This will reduce the number of issued instruction for several avx codes. llvm-svn: 136323
* movd/movq write zeros in the high 128-bit part of the vector. UseBruno Cardoso Lopes2011-07-281-2/+28
| | | | | | them to match 256-bit scalar_to_vector+zext. llvm-svn: 136322
* Add a few patterns to match allzeros without having to use the fp unit.Bruno Cardoso Lopes2011-07-281-0/+10
| | | | | | | Take advantage that the 128-bit vpxor zeros the higher part and use it. This also fixes PR10491 llvm-svn: 136321
* Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also moveBruno Cardoso Lopes2011-07-282-7/+13
| | | | | | a convert pattern close to the instruction definition. llvm-svn: 136320
* Refactor and improve the encodings/decodings for addrmode3 loads, and make ↵Owen Anderson2011-07-273-23/+41
| | | | | | the writeback operand always the first. llvm-svn: 136295
* Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng2011-07-274-23/+15
| | | | | | | | | This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 llvm-svn: 136292
* Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.Kevin Enderby2011-07-273-4/+35
| | | | | | | | | | | | llvm-mc gives an "invalid operand" error for instructions that take an unsigned immediate which have the high bit set such as: pblendw $0xc5, %xmm2, %xmm1 llvm-mc treats all x86 immediates as signed values and range checks them. A small number of x86 instructions use the imm8 field as a set of bits. This change only changes those instructions and where the high bit is not ignored. The others remain unchanged. llvm-svn: 136287
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