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* [Hexagon] Generate store-immediate instructions for stack objectsKrzysztof Parzyszek2017-06-132-4/+25
* [Hexagon] Generate multiply-high instruction in iselKrzysztof Parzyszek2017-06-131-0/+5
* bpf: clang-format on BPFAsmPrinter.cppYonghong Song2017-06-131-2/+3
* [Hexagon] Don't kill live registers when creating mux out of tfrKrzysztof Parzyszek2017-06-132-8/+22
* [MIPS] BuildCondBr should preserve MO flagsSimon Dardis2017-06-131-6/+3
* [Hexagon] Stop pmpy recognition when shift conversion failsKrzysztof Parzyszek2017-06-131-1/+2
* [ARM] Add scheduling classes for VFNM[AS]Oliver Stannard2017-06-131-6/+12
* Strip UTF8 BOM that got added in rL305091Simon Pilgrim2017-06-131-1/+0
* [X86][SSE] Refactor getTargetConstantBitsFromNode to avoid large APInts (PR32...Simon Pilgrim2017-06-131-36/+66
* PPCISelLowering.cpp: Fix warnings in r305214. [-Wdocumentation]NAKAMURA Takumi2017-06-131-3/+3
* [AVX-512] Mark masked VPCMP instructions as commutable.Craig Topper2017-06-132-14/+27
* [AVX-512] Mark masked version of vpcmpeq as being commutable.Craig Topper2017-06-131-0/+1
* [X86] Add masked integer compare instructions to load folding tables.Craig Topper2017-06-131-0/+58
* [WebAssembly] Fix symbol type for addresses of external functionsSam Clegg2017-06-131-2/+8
* AMDGPU/GlobalISel: Mark 32-bit G_ADD as legalTom Stellard2017-06-121-0/+2
* AArch64: don't try to emit an add (shifted reg) for SP.Tim Northover2017-06-121-0/+8
* [PowerPC] Match vec_revb builtins to P9 instructions.Tony Jiang2017-06-124-7/+105
* [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.Tony Jiang2017-06-124-5/+51
* AMDGPU: Don't add same implicit use multiple timesMatt Arsenault2017-06-121-4/+2
* AMDGPU: Teach isLegalAddressingMode about flat offsetsMatt Arsenault2017-06-121-3/+11
* AMDGPU: Start selecting flat instruction offsetsMatt Arsenault2017-06-122-18/+42
* AMDGPU: Verify that flat offsets aren't used pre-GFX9Matt Arsenault2017-06-121-2/+11
* [Falkor] Enable SW Prefetch.Haicheng Wu2017-06-121-0/+4
* AMDGPU: Start adding offset fields to flat instructionsMatt Arsenault2017-06-125-25/+94
* [DAG] add helper to bind memop chains; NFCISanjay Patel2017-06-122-34/+4
* Const correctness for TTI::getRegisterBitWidthDaniel Neilson2017-06-1210-10/+10
* [X86][SSE] Change memop fragment to inherit from vec128load with local alignm...Simon Pilgrim2017-06-121-8/+4
* [AVX-512] Add VPCONFLICT and VPLZCNT to load folding tables.Craig Topper2017-06-121-0/+36
* [x86] use vperm2f128 rather than vinsertf128 when there's a chance to fold a ...Sanjay Patel2017-06-111-9/+13
* AMDGPU : Fix ISA Version Definitions.Wei Ding2017-06-104-27/+99
* [AArch64] Add fallback in FastISel fp16 conversionsI-Jui (Ray) Sung2017-06-091-1/+5
* [AMDGPU] Add intrinsics for alignbit and alignbyte instructionsStanislav Mekhanoshin2017-06-091-2/+2
* [X86][SSE] Add support for PACKSS nodes to faux shuffle extractionSimon Pilgrim2017-06-091-6/+32
* [Hexagon] Fixes and updates to the selection patternsKrzysztof Parzyszek2017-06-091-28/+52
* Reland "[SelectionDAG] Enable target specific vector scalarization of calls a...Simon Dardis2017-06-096-15/+194
* [AMDGPU] Fix for issue in alloca to vector promotion passDavid Stuttard2017-06-091-6/+12
* [ARM] Custom machine-scheduler. NFCI.Javed Absar2017-06-091-0/+15
* [Hexagon] Add LLVM header to HexagonPatterns.tdKrzysztof Parzyszek2017-06-091-0/+9
* [ARM] Add scheduling info for VFMSOliver Stannard2017-06-091-3/+6
* Test commit: remove whitespaceStefan Maksimovic2017-06-091-1/+1
* Fix -Wunused-variable.Rui Ueyama2017-06-091-2/+0
* [Hexagon] Re-enable machine verifier after codegen passesKrzysztof Parzyszek2017-06-081-17/+17
* [Hexagon] Skip mux generation when predicate register is undefinedKrzysztof Parzyszek2017-06-081-1/+4
* AMDGPU: Work around build special casing .inc filesMatt Arsenault2017-06-083-1/+7
* AMDGPU: Use correct register names in inline assemblyMatt Arsenault2017-06-083-0/+410
* [Hexagon] Speedup NumNodesBlocking calculation. NFCI.Nirav Dave2017-06-081-32/+25
* [PPC] In PPCBoolRetToInt change the bool value to i64 if the target is ppc64Guozhi Wei2017-06-081-12/+26
* [AMDGPU] Force qsads instrs to use different dest register than source registersMark Searles2017-06-081-0/+5
* [Power9] Exploit vector integer extend instructionsZaara Syeda2017-06-081-0/+51
* Add scheduler classes to integer/float horizontal operations.Andrew V. Tischenko2017-06-086-5/+126
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