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* Revert r318678 to fix Clang testRichard Trieu2017-11-215-16/+20
| | | | | | r318678 caused the Clang test CodeGen/ms-inline-asm.c to start failing. llvm-svn: 318710
* [Sparc] efficient pattern for UINT_TO_FP conversionFedor Sergeev2017-11-203-29/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: while investigating performance degradation of imagick benchmark there were found inefficient pattern for UINT_TO_FP conversion. That pattern causes RAW hazard in assembly code. Specifically, uitofp IR operator results in poor assembler : st %i0, [%fp - 952] ldd [%fp - 952], %f0 it stores 32-bit integer register into memory location and then loads 64-bit floating point data from that location. That is exactly RAW hazard case. To optimize that case it is possible to use SPISD::ITOF and SPISD::XTOF for conversion from integer to floating point data type and to use ISD::BITCAST to copy from integer register into floating point register. The fix is to write custom UINT_TO_FP pattern using SPISD::ITOF, SPISD::XTOF, ISD::BITCAST. Patch by Alexey Lapshin Reviewers: fedor.sergeev, jyknight, dcederman, lero_chris Reviewed By: jyknight Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36875 llvm-svn: 318704
* Fix spelling in comment. NFCI.Simon Pilgrim2017-11-201-1/+1
| | | | llvm-svn: 318687
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-201-2/+4
| | | | | | Fix the modeling of test and branch. llvm-svn: 318685
* [X86] Avoid unecessary opsize byte in segment move to memoryNirav Dave2017-11-205-20/+16
| | | | | | | | | | | | | | | | | Summary: Segment moves to memory are always 16-bit. Remove invalid 32 and 64 bit variants. Fixes PR34478. Reviewers: rnk, craig.topper Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39847 llvm-svn: 318678
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer ↵Dmitry Preobrazhensky2017-11-207-100/+149
| | | | | | | | | | | | v_{add/addc/sub/subrev/subb/subbrev} See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765 Reviewers: tamazov, SamWot, arsenm, vpykhtin Differential Revision: https://reviews.llvm.org/D40088 llvm-svn: 318675
* [mips] Reorder target specific passesSimon Dardis2017-11-201-5/+4
| | | | | | | | | Move the hazard scheduling pass to after the long branch pass, as the long branch pass can create forbiddden slot hazards. Rather than complicating the implementation of the long branch pass to handle forbidden slot hazards, just reorder the passes. llvm-svn: 318657
* [SystemZ] Bugfix for handling of subregisters in getRegAllocationHints().Jonas Paulsson2017-11-201-2/+4
| | | | | | | | The 32 bit subreg indices of GR128 registers must also be checked for in getRC32(). Review: Ulrich Weigand. llvm-svn: 318652
* [PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.Tony Jiang2017-11-205-46/+158
| | | | | | | | | | | | | | | | | | | | The VSX versions have the advantage of a full 64-register target whereas the FP ones have the advantage of lower latency and higher throughput. So what we’re after is using the faster instructions in low register pressure situations and using the larger register file in high register pressure situations. The heuristic chooses between the following 7 pairs of instructions. PPC::LXSSPX vs PPC::LFSX PPC::LXSDX vs PPC::LFDX PPC::STXSSPX vs PPC::STFSX PPC::STXSDX vs PPC::STFDX PPC::LXSIWAX vs PPC::LFIWAX PPC::LXSIWZX vs PPC::LFIWZX PPC::STXSIWX vs PPC::STFIWX Differential Revision: https://reviews.llvm.org/D38486 llvm-svn: 318651
* [AArch64][TableGen] Skip tied result operands for InstAliasSander de Smalen2017-11-201-16/+16
| | | | | | | | | | | | | | | | | | | | Summary: This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias. This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch. Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka Reviewed By: rengolin, SjoerdMeijer Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D40030 llvm-svn: 318650
* AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG ↵Valery Pykhtin2017-11-205-4/+431
| | | | | | | | (experimental) Differential revision: https://reviews.llvm.org/D39897 llvm-svn: 318649
* [LV][X86] Support of AVX2 Gathers code generation and update the LV with thisMohammed Agabaria2017-11-205-46/+172
| | | | | | | | | | | | | | | This patch depends on: https://reviews.llvm.org/D35348 Support of pattern selection of masked gathers of AVX2 (X86\AVX2 code gen) Update LoopVectorize to generate gathers for AVX2 processors. Reviewers: delena, zvi, RKSimon, craig.topper, aaboud, igorb Reviewed By: delena, RKSimon Differential Revision: https://reviews.llvm.org/D35772 llvm-svn: 318641
* [X86] Add test cases for rndscaless/sd intrinsics.Craig Topper2017-11-191-1/+1
| | | | | | Also fix the memop in the ins for these instructions. Not sure what effect this has. llvm-svn: 318624
* [X86] Improve load folding of scalar rcp28 and rsqrt28 instructions using ↵Craig Topper2017-11-191-3/+2
| | | | | | sse_load_f32/f64. llvm-svn: 318623
* [bpf] remove unused variableAlexei Starovoitov2017-11-191-1/+0
| | | | | Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 318615
* [bpf] allow direct and indirect callsAlexei Starovoitov2017-11-195-8/+25
| | | | | | | | | | | | | | | kernel verifier is becoming smarter and soon will support direct and indirect function calls. Remove obsolete error from BPF backend. Make call to use PCRel_4 fixup. 'bpf to bpf' calls are distinguished from 'bpf to kernel' calls by insn->src_reg == BPF_PSEUDO_CALL == 1 which is used as relocation indicator similar to ld_imm64->src_reg == BPF_PSEUDO_MAP_FD == 1 The actual 'call' instruction remains the same for both 'bpf to kernel' and 'bpf to bpf' calls. Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 318614
* [X86] Switch cannonlake to use the SkylakeServer scheduling model instead of ↵Craig Topper2017-11-191-1/+1
| | | | | | | | Haswell. Cannonlake comes after skylake and supports avx512 so this is probably a closer model for now. llvm-svn: 318613
* [X86] Add skeleton support for icelake CPU.Craig Topper2017-11-192-1/+14
| | | | | | There are several patches out for review right now to implement Icelake features. This adds a CPU to collect them under. llvm-svn: 318612
* [X86] Fix 80 column violation and remove trailing whitespace. NFCCraig Topper2017-11-191-7/+8
| | | | llvm-svn: 318611
* [X86] Simplify the gather/scatter isel predicates.Craig Topper2017-11-181-54/+27
| | | | | | We don't need a dyn_cast, the predicate already specified the base node. We only need to check the type of the index, the base ptr is guaranteed to be scalar. llvm-svn: 318596
* [X86] Qualify a few places with ExperimentalVectorWideningLegalization.Craig Topper2017-11-181-4/+8
| | | | | | I'm playing around with this flag and these places cause errors if not qualified. llvm-svn: 318595
* [X86] Add todo comment for TRUNC(SUB(X,C)) -> SUB(TRUNC(X),C')Simon Pilgrim2017-11-181-0/+1
| | | | | | As discussed on PR35295, but it causes regressions in combineSubToSubus which need to be addressed first llvm-svn: 318594
* [X86] Output cfi directives for saved XMM registers even if no GPRs are savedMartin Storsjo2017-11-181-2/+1
| | | | | | | | | | This makes sure that functions that only clobber xmm registers (on win64) also get the right cfi directives, if dwarf exceptions are enabled. Differential Revision: https://reviews.llvm.org/D40191 llvm-svn: 318591
* [X86] Fix typo in variable name. NFCCraig Topper2017-11-181-4/+4
| | | | llvm-svn: 318590
* [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPRQuentin Colombet2017-11-181-2/+11
| | | | | | | | | We used to detect loads feeding fp instructions, but we were failing to take into account cases where this happens through copies. For instance, loads can fed copies coming from the ABI lowering of floating point arguments/results. llvm-svn: 318589
* [AArch64] Map G_STORE on FPR when the source comes from a FPR copyQuentin Colombet2017-11-181-1/+9
| | | | | | | | | We used to detect that stores were fed by fp instructions, but we were failing to take into account cases where this happens through copies. For instance, stores can be fed by copies coming from the ABI lowering of floating point arguments. llvm-svn: 318588
* [AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 ↵Quentin Colombet2017-11-181-4/+5
| | | | | | | | | cross copies Turns out this copies can actually occur because of the way we lower the ABI for half. llvm-svn: 318586
* AMDGPU: Move hazard avoidance out of waitcnt pass.Matt Arsenault2017-11-174-93/+60
| | | | | | | | | | This is mostly moving VMEM clause breaking into the hazard recognizer. Also move another hazard currently handled in the waitcnt pass. Also stops breaking clauses unless xnack is enabled. llvm-svn: 318557
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-171-43/+78
| | | | | | Improve the accuracy of the model by specifying the proper number of uops. llvm-svn: 318531
* [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*Dmitry Preobrazhensky2017-11-175-26/+26
| | | | | | | | | | See bug 35148: https://bugs.llvm.org//show_bug.cgi?id=35148 Reviewers: tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D39492 llvm-svn: 318526
* [ARM] Use dwarf exception handling on MinGWMartin Storsjo2017-11-172-3/+10
| | | | | | | | | | | | | | | Enabling and using dwarf exceptions seems like an easier path to take, than to make the COFF/ARM backend output EHABI directives. Previously, no EH model was enabled at all on this target. There's no point in setting UseIntegratedAssembler to false since GNU binutils doesn't support Windows on ARM, and since we don't need to support external assembler, we don't need to use register numbers in cfi directives. Differential Revision: https://reviews.llvm.org/D39532 llvm-svn: 318510
* AMDGPU: Replace list of SMEM buffer opcodesMatt Arsenault2017-11-172-10/+14
| | | | llvm-svn: 318506
* AMDGPU: Fix breaking SMEM clausesMatt Arsenault2017-11-172-25/+45
| | | | | | | | This was completely ignoring subregisters, so was not very useful. Also only break them if xnack is actually enabled. llvm-svn: 318505
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-17213-288/+288
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* [ARM] 't' asm constraint should accept i32Yi Kong2017-11-161-1/+1
| | | | | | | | | | | | | | | | | | | | 't' constraint normally only accepts f32 operands, but for VCVT the operands can be i32. LLVM is overly restrictive and rejects asm like: float foo() { float result; __asm__ __volatile__( "vcvt.f32.s32 %[result], %[arg1]\n" : [result]"=t"(result) : [arg1]"t"(0x01020304) ); return result; } Relax the value type for 't' constraint to either f32 or i32. Differential Revision: https://reviews.llvm.org/D40137 llvm-svn: 318472
* [X86] Add DAG combine to remove sext i32->i64 from gather/scatter instructions.Craig Topper2017-11-161-1/+22
| | | | | | | | | | Only do this pre-legalize in case we're using the sign extend to legalize for KNL. This recovers all of the tests that changed when I stopped SelectionDAGBuilder from deleting sign extends. There's more work that could be done here particularly to fix the i8->i64 test case that experienced split. llvm-svn: 318468
* [RISCV] Fix 64-bit data layout mismatch between backend and target descriptionMandeep Singh Grang2017-11-161-1/+1
| | | | | | | | | | | | Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, llvm-commits Differential Revision: https://reviews.llvm.org/D40145 llvm-svn: 318454
* [X86] Pre-truncate gather/scatter indices that have element sizes larger ↵Craig Topper2017-11-161-2/+19
| | | | | | | | | | than 64-bits before Legalize. The wider element type will normally cause legalize to try to split and scalarize the gather/scatter, but we can't handle that. Instead, truncate the index early so the gather/scatter node is insulated from the legalization. This really shouldn't happen in practice since InstCombine will normalize index types to the same size as pointers. llvm-svn: 318452
* [X86] DAGCombinerInfo is in TargetLowering not X86TargetLowering.Craig Topper2017-11-161-1/+1
| | | | llvm-svn: 318451
* [arc] Fix ambiguous overloaded operator errorDaniel Sanders2017-11-161-1/+1
| | | | | | | | lib/Target/ARC/ARCISelLowering.cpp:490:22: error: use of overloaded operator '<<' is ambiguous (with operand types 'llvm::raw_ostream' and 'llvm::MVT::SimpleValueType') << RegVT.getSimpleVT().SimpleTy << "\n"); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ llvm-svn: 318443
* bpf: print backward branch target properlyYonghong Song2017-11-164-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | Currently, it prints the backward branch offset as unsigned value like below: 7: 7d 34 0b 00 00 00 00 00 if r4 s>= r3 goto 11 <LBB0_3> 8: b7 00 00 00 00 00 00 00 r0 = 0 LBB0_2: 9: 07 00 00 00 01 00 00 00 r0 += 1 ...... 17: bf 31 00 00 00 00 00 00 r1 = r3 18: 6d 32 f6 ff 00 00 00 00 if r2 s> r3 goto 65526 <LBB0_3+0x7FFB0> The correct print insn 18 should be: 18: 6d 32 f6 ff 00 00 00 00 if r2 s> r3 goto -10 <LBB0_2> To provide better clarity and be consistent with kernel verifier output, the insn 7 output is changed to the following with "+" added to non-negative branch offset: 7: 7d 34 0b 00 00 00 00 00 if r4 s>= r3 goto +11 <LBB0_3> Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 318442
* [arc] Update TargetInfo to include the new backend name argumentDaniel Sanders2017-11-161-1/+1
| | | | | | | Also update a comment about the usage of RegisterTarget() that didn't mention the new argument. llvm-svn: 318441
* Fix RISCV build after r318352Azharuddin Mohammed2017-11-161-2/+2
| | | | | | | | | | | | Reviewers: asb, apazos, mgrang Reviewed By: mgrang Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, llvm-commits Differential Revision: https://reviews.llvm.org/D40139 llvm-svn: 318437
* [PPC] Change i32 constant in store instruction to i64Guozhi Wei2017-11-161-1/+16
| | | | | | | | This patch changes all i32 constant in store instruction to i64 with truncation, to increase the chance that the referenced constant can be shared with other i64 constant. Differential Revision: https://reviews.llvm.org/D39352 llvm-svn: 318436
* [TTI][X86] update costs of interleaved load\store of i64\doubleMohammed Agabaria2017-11-161-0/+6
| | | | | | | | | | | | This patch contains more accurate cost of interelaved load\store of stride 2 for the types int64\double on AVX2. Reviewers: delena, RKSimon, craig.topper, dorit Reviewed By: dorit Differential Revision: https://reviews.llvm.org/D40008 llvm-svn: 318385
* [X86] Update TTI to report that v1iX/v1fX types aren't legal for masked ↵Craig Topper2017-11-161-2/+10
| | | | | | | | gather/scatter/load/store. The type legalizer will try to scalarize these operations if it sees them, but there is no handling for scalarizing them. This leads to a fatal error. With this change they will now be scalarized by the mem intrinsic scalarizing pass before SelectionDAG. llvm-svn: 318380
* Fix thinko in last commit.Eric Christopher2017-11-161-1/+1
| | | | llvm-svn: 318374
* Add NDEBUG checks around LLVM_DUMP_METHOD functions for Wunused-function ↵Eric Christopher2017-11-162-2/+8
| | | | | | warnings. llvm-svn: 318373
* [X86] Custom type legalize v2f32 masked gathers instead of trying to cleanup ↵Craig Topper2017-11-161-26/+28
| | | | | | after type legalization. llvm-svn: 318368
* bpf: enable llvm-objdump to print out symbolized jmp targetYonghong Song2017-11-161-0/+34
| | | | | | | | | | | | | | | | | | Add hook in BPF backend so that llvm-objdump can print out the jmp target with label names, e.g., ... if r1 != 2 goto 6 <LBB0_2> ... goto 7 <LBB0_4> ... LBB0_2: ... LBB0_4: ... Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 318358
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