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* AMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCEMatt Arsenault2015-11-021-23/+89
| | | | | | | Make the REG_SEQUENCE be a VGPR, and do the register class copy first. llvm-svn: 251855
* [PPC64LE] Properly initialize instr-info in PPCVSXSwapRemoval passBill Schmidt2015-11-021-1/+1
| | | | | | | | Replace some hacky code with the proper way to get at this data. No functional change. llvm-svn: 251848
* WatchOS: update default CPU for triple after t2dsp -> dsp renameTim Northover2015-11-021-2/+2
| | | | llvm-svn: 251814
* Fix for bootstrap bug introduced in r244921Nemanja Ivanovic2015-11-022-3/+2
| | | | | | | | | | This revision has introduced an issue that only affects bootstrapped compiler when it is printing the ASM. It turns out that the new code path taken due to legalizing a scalar_to_vector of i64 -> v2i64 exposes a missing check in a micro optimization to change a load followed by a scalar_to_vector into a load and splat instruction on PPC. llvm-svn: 251798
* AVX512: Implemented encoding and intrinsics for VBROADCASTI32x2 and ↵Igor Breger2015-11-023-0/+54
| | | | | | | | VBROADCASTF32x2 instructions. Differential Revision: http://reviews.llvm.org/D14216 llvm-svn: 251781
* [X86] Remove assertions that check for valid scale values on scatter/gather ↵Craig Topper2015-11-021-8/+0
| | | | | | intrinsics. Nothing upstream prevented illegal values from getting here. llvm-svn: 251780
* [X86] Fold 'if' followed by just an llvm_unreachable into an assert.Craig Topper2015-11-021-8/+7
| | | | llvm-svn: 251778
* [X86] Use isa instead of dyn_cast in a bool context. NFCCraig Topper2015-11-021-2/+2
| | | | llvm-svn: 251777
* [X86] Remove some llvm_unreachables after switches that already have an ↵Craig Topper2015-11-021-5/+3
| | | | | | unreachable in their default case. llvm-svn: 251776
* [X86] Remove a 'break' after an llvm_unreachable.Craig Topper2015-11-021-3/+1
| | | | llvm-svn: 251775
* [X86] Use cast instead of dyn_cast and a null check marked unreachable.Craig Topper2015-11-021-8/+3
| | | | llvm-svn: 251774
* [X86] Use MVT instead of EVT when the type is known to be simple. NFCCraig Topper2015-11-022-89/+80
| | | | llvm-svn: 251772
* Untabify.NAKAMURA Takumi2015-11-023-7/+7
| | | | llvm-svn: 251769
* AVX-512: Optimized SIMD truncate operations for AVX512F set.Elena Demikhovsky2015-11-012-3/+23
| | | | | | | | | | | | Optimized <8 x i32> to <8 x i16> <4 x i64> to < 4 x i32> <16 x i16> to <16 x i8> All these oprtrations use now AVX512F set (KNL). Before this change it was implemented with AVX2 set. Differential Revision: http://reviews.llvm.org/D14108 llvm-svn: 251764
* [X86] Replace getScalarType with getVectorElementType when the type is ↵Craig Topper2015-10-311-29/+29
| | | | | | already known to be a vector. This should result in slightly less code. NFC llvm-svn: 251751
* [X86] Convert to MVT instead of calling EVT functions since we already know ↵Craig Topper2015-10-311-2/+2
| | | | | | the type is simple. NFC llvm-svn: 251745
* [X86] Call getScalarSizeInBits() instead of ↵Craig Topper2015-10-311-5/+5
| | | | | | getScalarType().getScalarSizeInBits(). NFC llvm-svn: 251744
* [X86] Remove two const references to the return value of a constructor and ↵Craig Topper2015-10-311-2/+2
| | | | | | just use normal object creation syntax. NFC llvm-svn: 251743
* [X86] Replace EVT with MVT in some more places. NFCCraig Topper2015-10-311-12/+12
| | | | llvm-svn: 251742
* [X86] Fix indentation of case statements in switch. NFCCraig Topper2015-10-311-16/+16
| | | | llvm-svn: 251741
* [X86] Reduce math for index calculation for inserting and extracting ↵Craig Topper2015-10-311-14/+16
| | | | | | subvectors and elements by exploiting the fact that all supported vector types have a power 2 number of elements. llvm-svn: 251740
* [WebAssembly] Fix import statementJF Bastien2015-10-301-9/+10
| | | | | | | | | | Summary: Imports should be generated like (param i32 f32...) not (param i32) (param f32) ... Author: binji Reviewers: jfb Subscribers: jfb, dschuff llvm-svn: 251714
* [X86] Use is128BitVector/is256BitVector/is512BitVector in place of ↵Craig Topper2015-10-301-17/+16
| | | | | | getSizeInBits == in some places. NFC llvm-svn: 251687
* [X86] Minor formatting fixes. NFC.Craig Topper2015-10-301-9/+8
| | | | llvm-svn: 251686
* [X86] Use MVT instead of EVT in some places. NFCCraig Topper2015-10-301-37/+41
| | | | | | Prior to this the compiled code probably had extra checks for extended types that won't ever execute. llvm-svn: 251682
* [X86][SSE] Shuffle blends with zeroSimon Pilgrim2015-10-291-19/+49
| | | | | | | | This patch generalizes the zeroing of vector elements with the BLEND instructions. Currently a zero vector will only blend if the shuffled elements are correctly inline, this patch recognises when a vector input is zero (or zeroable) and modifies a local copy of the shuffle mask to support a blend. As a zeroable vector input may not be all zeroes, the zeroable vector is regenerated if necessary. Differential Revision: http://reviews.llvm.org/D14050 llvm-svn: 251659
* [SystemZ] Make the CCRegs regclass non-allocatable.Jonas Paulsson2015-10-293-4/+6
| | | | | | | | | | | | | | | | | | | | | This was discovered to be necessary while running memchr-01.ll with -verify-machinstrs, because it is not allowed to have a phys reg live accross block boundaries while on SSA form, if the register is allocatable (expect in entry block and landing pads). In this test case, stringRRE pseudos are expanded after isel by adding a loop block which produces a live out CC register. To make the test pass, it was also necessary to not say that StringRRELoop pseudo uses R0L, this is only true for the StringRRE opcode. -verify-machineinstrs added to memchr-01.ll test. New test case int-cmp-51.ll to test that MachineCSE can eliminate an identical compare (which it couldn't do before). Reviewed by Ulrich Weigand llvm-svn: 251634
* AMDGPU/SI: handle undef for llvm.SI.packf16Marek Olsak2015-10-291-0/+4
| | | | llvm-svn: 251632
* AMDGPU/SI: use S_OR for fneg (fabs f32)Marek Olsak2015-10-291-2/+1
| | | | llvm-svn: 251631
* AMDGPU/SI: use S_AND for i1 truncMarek Olsak2015-10-291-2/+2
| | | | llvm-svn: 251630
* [mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is usedZoran Jovanovic2015-10-291-5/+10
| | | | | | | | | | | | | | | Summary: This commit resolves wrong opcodes for ll and sc instructions for r6 architecutres, which were generated in method MipsTargetLowering::emitAtomicBinary. Author: Jelena.Losic Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D13593 llvm-svn: 251629
* Recognize that ARM1176JZ[F]-S support TrustZoneArtyom Skrobov2015-10-292-1/+4
| | | | | | | | | | | | | | Summary: ARMv6KZ cores were set up incorrectly in ARM.td; also, the SMI mnemonic (the old name for SMC, as defined in ARMv6KZ) wasn't supported. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14154 llvm-svn: 251627
* [mips] Check the register class before replacing materializations of zero ↵Vasileios Kalintiris2015-10-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | with $zero in microMIPS. Summary: The microMIPS register class GPRMM16 does not contain the $zero register. However, MipsSEDAGToDAGISel::replaceUsesWithZeroReg() would replace uses of the $dst register: [d]addiu, $dst, $zero, 0 with the $zero register, without checking for membership in the register class of the target machine operand. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13984 llvm-svn: 251622
* [WebAssembly] Update opcode name format for conversionsJF Bastien2015-10-292-27/+35
| | | | | | | | | | | | Summary: Conversion opcode name format should be f64.convert_u/i64 not f64_convert_u Author: s3ththompson Reviewers: jfb Subscribers: sunfish, jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D14160 llvm-svn: 251613
* Remove CRLF line endings.Benjamin Kramer2015-10-291-6/+6
| | | | llvm-svn: 251594
* [PowerPC] Recurse through constants when looking for TLS globalsHal Finkel2015-10-281-2/+10
| | | | | | | | | | | | | We cannot form ctr-based loops around function calls, including calls to __tls_get_addr used for PIC TLS variables. References to such TLS variables, however, might be buried within constant expressions, and so we need to search the entire constant expression to be sure that no references to such TLS variables exist. Fixes PR25256, reported by Eric Schweitz. This is a slightly-modified version of the patch suggested by Eric in the bug report, and a test case I created. llvm-svn: 251582
* [PowerPC] Don't return unsupported register classes for asm constraintsHal Finkel2015-10-281-5/+6
| | | | | | | | | As a follow-up to r251566, do the same for the other optionally-supported register classes (mostly for vector registers). Don't return an unavailable register class (which would cause an assert later), but fail cleanly when provided an unsupported inline asm constraint. llvm-svn: 251575
* ARM: add support for WatchOS's compact unwind information.Tim Northover2015-10-286-9/+240
| | | | llvm-svn: 251573
* ARM: teach backend about WatchOS and TvOS libcalls.Tim Northover2015-10-282-24/+48
| | | | | | | The most substantial changes are again for watchOS: libcalls are hard-float if needed and sincos has a different calling convention. llvm-svn: 251571
* ARM: add backend support for the ABI used in WatchOSTim Northover2015-10-288-16/+42
| | | | | | | At the LLVM level this ABI is essentially a minimal modification of AAPCS to support 16-byte alignment for vector types and the stack. llvm-svn: 251570
* ARM: support .watchos_version_min and .tvos_version_min.Tim Northover2015-10-281-1/+9
| | | | | | | | These MachO file directives are used by linkers and other tools to provide compatibility information, much like the existing .ios_version_min and .macosx_version_min. llvm-svn: 251569
* [PowerPC] Cleanly reject asm crbit constraint with -crbitsHal Finkel2015-10-281-1/+2
| | | | | | | When crbits are disabled, cleanly reject the constraint (return the register class only to cause an assert later). llvm-svn: 251566
* [X86] A small fix in X86/X86TargetTransformInfo.cpp: check a value type is ↵Cong Hou2015-10-281-1/+2
| | | | | | simple before calling getSimpleVT(). llvm-svn: 251538
* [ARM] Allow SP in rGPR, starting from ARMv8Artyom Skrobov2015-10-282-13/+36
| | | | | | | | | | | | | | | | | Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
* Put global classes into the appropriate namespace.Benjamin Kramer2015-10-284-6/+9
| | | | | | | Most of the cases belong into an anonymous namespace. No functionality change intended. llvm-svn: 251515
* [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI ↵Hrvoje Varga2015-10-286-7/+158
| | | | | | | | and WAIT instructions Differential Revision: http://reviews.llvm.org/D12628 llvm-svn: 251510
* [X86] Make some for loops over MVTs more explicit (and shorter) by just ↵Craig Topper2015-10-281-42/+7
| | | | | | mentioning all the relevant types in an initializer list. NFC llvm-svn: 251500
* Use range-based for loops and use initializer list to remove a small static ↵Craig Topper2015-10-281-7/+5
| | | | | | array. NFC llvm-svn: 251494
* Remove templates from CostTableLookup functions. All instantiations had the ↵Craig Topper2015-10-283-46/+36
| | | | | | | | same type. This also lets us remove the versions of the functions that took a statically sized array as we can rely on ArrayRef implicit conversion now. llvm-svn: 251490
* [PowerPC] Replace cntlz[.] with cntlzw[.]Hal Finkel2015-10-281-2/+5
| | | | | | | | | | | | | | | | | | | cntlz is the old POWER mnemonic. cntlzw is the PowerPC mnemonic. This change fixes an issue when -no-integrated-as: The opcode cntlz is unrecognized by gas Alias the POWER mnemonic cntlz[.] to the PowerPC mnemonic cntlzw[.] This is done for because the POWER cntlz mnemonic has be used by LLVM for a very long time. We need to make sure that assembly programs that are using the cntlz[.] do not break with this change. Change PowerPC tests to reflect the insn change from cntlz to cntlzw. Add assembly test to verify cntlz[.] is encoded correctly. Patch by Tom Rix! llvm-svn: 251489
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