summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* Use sdmem and sse_load_f64 (etc.) for the vectorDale Johannesen2010-08-071-8/+13
| | | | | | | | form of CMPSD (etc.) Matching a 128-bit memory operand is wrong, the instruction uses only 64 bits (same as ADDSD etc.) 8193553. llvm-svn: 110491
* Patterns to match AVX 256-bit vzero intrinsicsBruno Cardoso Lopes2010-08-061-4/+4
| | | | llvm-svn: 110480
* Patterns to match AVX 256-bit permutation intrinsicsBruno Cardoso Lopes2010-08-062-13/+48
| | | | llvm-svn: 110468
* Remove empty processFunctionBeforeFrameFinalized(). The defaultJim Grosbach2010-08-062-6/+0
| | | | | | | implementation of the function is equivalent, so no need to provide the target-specific version until/unless it needs to do something. llvm-svn: 110465
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-0631-36/+36
| | | | llvm-svn: 110460
* Fix eabi calling convention when a 64 bit value shadows r3.Rafael Espindola2010-08-061-1/+1
| | | | | | | | | | | Without this what was happening was: * R3 is not marked as "used" * ARM backend thinks it has to save it to the stack because of vaarg * Offset computation correctly ignores it * Offsets are wrong llvm-svn: 110446
* Patterns to match AVX 256-bit horizontal arithmetic intrinsicsBruno Cardoso Lopes2010-08-061-14/+12
| | | | llvm-svn: 110427
* Patterns to match AVX 256-bit arithmetic intrinsicsBruno Cardoso Lopes2010-08-061-30/+75
| | | | llvm-svn: 110425
* Add the Optimize Compares pass (disabled by default).Bill Wendling2010-08-062-0/+67
| | | | | | | | | | | | | | | | This pass tries to remove comparison instructions when possible. For instance, if you have this code: sub r1, 1 cmp r1, 0 bz L1 and "sub" either sets the same flag as the "cmp" instruction or could be converted to set the same flag, then we can eliminate the "cmp" instruction all together. This is a important for ARM where the ALU instructions could set the CPSR flag, but need a special suffix ('s') to do so. llvm-svn: 110423
* Revert r110396 to fix buildbots.Owen Anderson2010-08-0631-36/+36
| | | | llvm-svn: 110410
* Add an option to always emit realignment code for a particular module.Eric Christopher2010-08-051-1/+34
| | | | llvm-svn: 110404
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-0531-36/+36
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMemDan Gohman2010-08-051-9/+3
| | | | | | to IntrReadWriteArgMem, as it's for reading as well as writing. llvm-svn: 110395
* Support very basic (doesn't include ABI support in the front-end, varags, ↵Bruno Cardoso Lopes2010-08-052-4/+30
| | | | | | ...) 256-bit argument passing and return for AVX llvm-svn: 110394
* Handle the memory barrier pseudo that goes to nothing for the JIT.Eric Christopher2010-08-051-1/+7
| | | | llvm-svn: 110371
* Set hasSideEffects on the 64-bit no-sse memory barrier.Eric Christopher2010-08-051-1/+1
| | | | llvm-svn: 110369
* For local variables in functions with a frame pointer, use FP as a baseJim Grosbach2010-08-052-18/+39
| | | | | | | | | | register for local access when it's closer to the stack slot being refererenced than the stack pointer. Make sure to take into account any argument frame SP adjustments that are in affect at the time. rdar://8256090 llvm-svn: 110366
* Fix indentation.Bob Wilson2010-08-051-6/+6
| | | | llvm-svn: 110363
* Add an ARM RSCrr instruction for disassembly only.Bob Wilson2010-08-051-0/+8
| | | | | | Partial fix for PR7792. llvm-svn: 110361
* Be a little bit more specific about target for the memory barrierEric Christopher2010-08-052-2/+4
| | | | | | instructions. llvm-svn: 110360
* Handle the pseudo in MCInstLower.Eric Christopher2010-08-051-0/+6
| | | | llvm-svn: 110359
* Add an ARM RSBrr instruction for disassembly only.Bob Wilson2010-08-051-1/+9
| | | | | | Partial fix for PR7792. llvm-svn: 110358
* Silence a GCC warning about && and || without explicit parentheses. ThisChandler Carruth2010-08-051-3/+3
| | | | | | | preserves the existing behavior, as it seems a concious choice to allow RS to be null and BigStack marked true. llvm-svn: 110307
* ARM "rrx" shift operands do not have an immediate. PR7790.Bob Wilson2010-08-052-24/+18
| | | | llvm-svn: 110292
* Make x86-64 membarriers work without sse and clean up some of theEric Christopher2010-08-043-4/+14
| | | | | | uses. llvm-svn: 110274
* and back in. false alarm on the tests from another unrelated local change.Jim Grosbach2010-08-041-2/+7
| | | | llvm-svn: 110269
* PR7814: Truncates cannot be ignored for signed comparisons.Eli Friedman2010-08-041-1/+2
| | | | llvm-svn: 110268
* Implement target specific getDebugValueLocation().Devang Patel2010-08-041-0/+13
| | | | llvm-svn: 110267
* oops. revert for a moment to clean up tests first.Jim Grosbach2010-08-041-7/+2
| | | | llvm-svn: 110259
* Reserve a stack slot if the function adjusts the stack but doesn'tJim Grosbach2010-08-041-2/+7
| | | | | | | | | | | simplify the call frame pseudo instructions. In that situation, the calculations for estimating the stack size will be way off, leading to not having an emergency spill slot when we need one. It should be possible to be more precise about tracking the adjustment values, but not really necessary for correctness. Upcoming cleanups for PEI in general will render that moot. llvm-svn: 110258
* Implement target specific getDebugValueLocation().Devang Patel2010-08-041-0/+14
| | | | llvm-svn: 110256
* Use indirect calls in PowerPC JIT.Torok Edwin2010-08-043-10/+31
| | | | | | | | | See PR5201. There is no way to know if direct calls will be within the allowed range for BL. Hence emit all calls as indirect when in JIT mode. Without this long-running applications will fail to JIT on PowerPC with a relocation failure. llvm-svn: 110246
* Remove switch for disabling ARM tail calls. TheyDale Johannesen2010-08-041-9/+0
| | | | | | seem to be working correctly. No functional change. llvm-svn: 110226
* Add DEBUG message.Devang Patel2010-08-041-0/+4
| | | | llvm-svn: 110224
* Enable COFF writer on mingw32 and cygwin.Benjamin Kramer2010-08-041-0/+2
| | | | llvm-svn: 110200
* Make SPU backend handle insertelement and Kalle Raiskila2010-08-043-2/+12
| | | | | | store for "half vectors" llvm-svn: 110198
* Print an error message when someone tries -integrated-as on an unsupported ↵Benjamin Kramer2010-08-041-1/+7
| | | | | | | | | | target. - The COFF backend doesn't support MingW/Cygwin at the moment, it'll report an error, but it's still much better than random assertions from the MachO backend. - We want to make ELF the default eventually, it's what the majority of targets use. llvm-svn: 110197
* by Alexander Herz:Gabor Greif2010-08-041-0/+7
| | | | | | | | | | | | "The CWriter::GetValueName() method does not check if a value as an alias and emits the alias name which will never be defined in the output .c file (so the output file fails to compile). This can happen if you have multiple inheritance with several destructors defined by clang (...D0Ev, ...D1Ev, ...D2Ev)." -- applied with minor tweaks. Thanks! llvm-svn: 110194
* Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABABob Wilson2010-08-041-0/+16
| | | | | | (absolute difference with accumulate) intrinsics. Radar 8228576. llvm-svn: 110170
* fix a win64 encoding problem, patch by Cameron Esfahani!Chris Lattner2010-08-031-1/+1
| | | | llvm-svn: 110164
* Add support for getting & setting the FPSCR application register on ARM when ↵Nate Begeman2010-08-034-20/+39
| | | | | | | | | VFP is enabled. Add support for using the FPSCR in conjunction with the vcvtr instruction, for controlling fp to int rounding. Add support for the FLT_ROUNDS_ node now that the FPSCR is exposed. llvm-svn: 110152
* CMake: Change somme target library names:Oscar Fuentes2010-08-032-2/+2
| | | | | | | | | | | XCore->XCoreGen PIC16->PIC16CodeGen After updating your working copy, the first build will fail because it is using the old library dependencies. Start the build again and it will work fine. llvm-svn: 110127
* More SPU v2f32 stuff added: insertelement and shuffle.Kalle Raiskila2010-08-022-0/+9
| | | | llvm-svn: 110038
* Add preliminary v2f32 support for SPU. Like with v2i32, we justKalle Raiskila2010-08-024-69/+81
| | | | | | | | duplicate the instructions and operate on half vectors. Also reorder code in SPUInstrInfo.td for better coherency. llvm-svn: 110037
* Add preliminary v2i32 support for SPU backend. As there are noKalle Raiskila2010-08-024-6/+49
| | | | | | | | | | such registers in SPU, this support boils down to "emulating" them by duplicating instructions on the general purpose registers. This adds the most basic operations on v2i32: passing parameters, addition, subtraction, multiplication and a few others. llvm-svn: 110035
* PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.Eli Friedman2010-08-021-3/+3
| | | | llvm-svn: 109998
* PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actuallyEli Friedman2010-08-011-2/+2
| | | | | | improves the generated code in some cases. llvm-svn: 109985
* Silence some -Asserts uninitialized variable warnings.Daniel Dunbar2010-07-311-2/+2
| | | | llvm-svn: 109956
* MC: Remove HasAbsolutizedSet from WindowsX86AsmBackend.Michael J. Spencer2010-07-311-1/+0
| | | | llvm-svn: 109949
* Move newlines before inline jumptables from the asm strings in .td files toBob Wilson2010-07-314-9/+9
| | | | | | | the jtblock_operand print methods. This avoids extra newlines in the disassembler's output. PR7757. llvm-svn: 109948
OpenPOWER on IntegriCloud