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* set SDNPVariadic on nodes throughout the rest of the targets thatChris Lattner2010-03-198-15/+27
| | | | | | need them. llvm-svn: 98937
* Remove a memory leak from ThumbTargetMachine.Jeffrey Yasskin2010-03-191-2/+6
| | | | llvm-svn: 98936
* add a new SDNPVariadic SDNP node flag, and use it inChris Lattner2010-03-191-4/+5
| | | | | | | | dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
* remove some damaged sign extend patterns that can never match.Chris Lattner2010-03-191-8/+6
| | | | llvm-svn: 98932
* disable some illegal blackfin patterns. sext from i32 to i32 can neverChris Lattner2010-03-191-5/+5
| | | | | | match. Jakob, please take a look when you get a chance. llvm-svn: 98931
* comment out a bunch of parallel store patterns that apparentlyChris Lattner2010-03-192-14/+44
| | | | | | | can't match or just have no testcases. Will remove after confirmation from dan that they really are dead. llvm-svn: 98930
* Fix -Asserts warnings.Daniel Dunbar2010-03-191-5/+4
| | | | llvm-svn: 98928
* X86: Fix encoding for TEST64rr.Daniel Dunbar2010-03-191-1/+1
| | | | llvm-svn: 98919
* Now that tblgen can handle matching implicit defs of instructionsChris Lattner2010-03-194-131/+104
| | | | | | | | | | | | | | | | | | | | | | | | | to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
* Update comment to refer to the right filename.Bob Wilson2010-03-181-1/+1
| | | | llvm-svn: 98902
* tidy upChris Lattner2010-03-181-2/+2
| | | | llvm-svn: 98901
* Get rid of target-specific fp <-> int nodes when still I'm here.Anton Korobeynikov2010-03-186-79/+69
| | | | llvm-svn: 98889
* Get rid of target-specific nodes for fp16 <-> fp32 conversion.Anton Korobeynikov2010-03-183-19/+11
| | | | llvm-svn: 98888
* Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass ↵Anton Korobeynikov2010-03-181-29/+39
| | | | | | copies weirdness more straightforward. Also, add GPR <-> SPR copy support. llvm-svn: 98887
* Couple of changes that Dan mentioned for llvm.stackprotector fast-isel.Eric Christopher2010-03-181-2/+2
| | | | llvm-svn: 98881
* X86MCCodeEmitter: Fix two minor issues with reloc_riprel_4byte_movq_load, weDaniel Dunbar2010-03-181-2/+4
| | | | | | | were missing it on some movq instructions and were not including the appropriate PCrel bias. llvm-svn: 98880
* fix some buggy ops concatentationChris Lattner2010-03-181-12/+12
| | | | llvm-svn: 98869
* use ins/outs.Chris Lattner2010-03-182-49/+49
| | | | llvm-svn: 98866
* outs come before ins.Chris Lattner2010-03-181-3/+3
| | | | llvm-svn: 98864
* Make fast-isel understand llvm.stackprotector.Eric Christopher2010-03-181-0/+15
| | | | llvm-svn: 98862
* Refactor NEON ld/st instructions to hardcode class arguments that are constants.Bob Wilson2010-03-181-201/+193
| | | | | | No functional changes. llvm-svn: 98860
* MC/X86/AsmMatcher: Use the new instruction cleanup routine to implement aDaniel Dunbar2010-03-182-3/+43
| | | | | | | | temporary workaround for matching inc/dec on x86_64 to the correct instruction. - This hack will eventually be replaced with a robust mechanism for handling matching instructions based on the available target features. llvm-svn: 98858
* fix an x86-64 encoding bug Daniel found.Chris Lattner2010-03-181-1/+4
| | | | llvm-svn: 98855
* add a special relocation type for movq loads for objectChris Lattner2010-03-182-4/+14
| | | | | | | files that produce special relocation types where the linker changes movq's into lea's. llvm-svn: 98839
* callq is pcrelativeChris Lattner2010-03-181-1/+1
| | | | llvm-svn: 98835
* Check if function names start with "llvm." before trying to lookup them up asBob Wilson2010-03-182-0/+8
| | | | | | | | intrinsics. The intrinsic lookup code assumes that this check has been done and assumes the names are at least 6 characters long. Valgrind complained about this. pr6638. llvm-svn: 98831
* Try to fix a valgrind error on 32 bit platforms: use %zu instead of %llu to ↵Benjamin Kramer2010-03-181-2/+2
| | | | | | format a size_t. llvm-svn: 98819
* Turning off post-ra scheduling for x86. It isn't a consistent win.Evan Cheng2010-03-182-15/+0
| | | | llvm-svn: 98810
* MC/Darwin: Add a new target hook for whether the target uses "reliable" ↵Daniel Dunbar2010-03-181-6/+7
| | | | | | | | symbol differences, basically whether the assembler should attempt to understand atoms when using scattered symbols. Also, avoid some virtual call overhead. llvm-svn: 98789
* X86 address mode matching code MatchAddressRecursively does some aggressive ↵Evan Cheng2010-03-171-14/+60
| | | | | | hack which require doing a RAUW. It may end up deleting some SDNode up stream. It should avoid referencing deleted nodes. llvm-svn: 98780
* Revert 98745 with respect to the addition of NEONFrm subformats for disassembly.Johnny Chen2010-03-172-453/+85
| | | | | | There is a better way coming up. llvm-svn: 98777
* Fixed a bug in the IT mask printing where T means the cond bit in the maskJohnny Chen2010-03-171-3/+5
| | | | | | | | | | | | | | matches that of Firstcond[0] and E means otherwise. The Firstcond[0] is also tagged in the Mask to facilitate Asm printing. The disassembler also depends on this arrangement. This is similar to what's described in A2.5.2 ITSTATE. Ran: utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2 successfully. llvm-svn: 98775
* Refines 98745 so that it only contains the patch related to the output of theJohnny Chen2010-03-171-12/+1
| | | | | | | | | addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. This patch removes the impl of printT2AddrModeImm8s4OffsetOperand() from ARMAsmPrinter.cpp. It is used by disassembler as of now. llvm-svn: 98774
* Clean up whitespace.Bob Wilson2010-03-171-16/+12
| | | | llvm-svn: 98769
* Increase format field from 5 to 6 bits. ARMII::FormMask was increased to 0x3fBob Wilson2010-03-171-3/+3
| | | | | | in svn r74988 but the format field was never widened. llvm-svn: 98768
* Initialize Size member to appease valgrind.Benjamin Kramer2010-03-171-1/+1
| | | | llvm-svn: 98763
* 98745 contains something unrelated to the patch.Johnny Chen2010-03-171-15/+1
| | | | | | Remove it from ARMAddressingModes.h. llvm-svn: 98751
* Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrmJohnny Chen2010-03-176-141/+930
| | | | | | | | | | | | | instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98745
* fix GetOrCreateTemporarySymbol to require a name, clientsChris Lattner2010-03-172-2/+2
| | | | | | | should use CreateTempSymbol() if they don't care about the name. llvm-svn: 98712
* Revert 98683. It is breaking something in the disassembler.Bob Wilson2010-03-168-62/+106
| | | | llvm-svn: 98692
* Remove redundant writeback flag from ARM address mode 6. Also remove theBob Wilson2010-03-168-106/+62
| | | | | | | optional register update argument, which is currently unused -- when we add support for that, it can just be a separate operand. llvm-svn: 98683
* reapply r98656 unmodified, which exposed the asmprinter not Chris Lattner2010-03-161-0/+25
| | | | | | handling constant unions. llvm-svn: 98680
* Disambiguate the *_UPD and * variants by specifying the writeback flag as 1.Johnny Chen2010-03-162-2/+10
| | | | | | | | | This is for the disassembly work. There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1. In such case, we'll use an adhoc approach to deduce the Opcode programmatically. llvm-svn: 98679
* Revert r98656, its breaking all over the place.Daniel Dunbar2010-03-161-25/+0
| | | | llvm-svn: 98662
* improve support for uniontype and ConstantUnion, patch by Tim Northover!Chris Lattner2010-03-161-0/+25
| | | | llvm-svn: 98656
* Remove redundant writeback flag in ARM addressing mode 5.Bob Wilson2010-03-166-23/+14
| | | | llvm-svn: 98648
* Remove the writeback flag from ARM's address mode 4. Now that we have separateBob Wilson2010-03-168-23/+11
| | | | | | instructions for ld/st with writeback, the flag is completely redundant. llvm-svn: 98643
* Fix unused variable warnings.Bob Wilson2010-03-162-2/+0
| | | | llvm-svn: 98642
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-1614-7355/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-1614-146/+7355
| | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
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