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* Revert "adding autoUpgrade support to broadcast[f|i]32x2 intrinsics"Uriel Korach2017-09-101-0/+10
| | | | | | This reverts commit r312879 - An accidental partial commit. llvm-svn: 312880
* adding autoUpgrade support to broadcast[f|i]32x2 intrinsicsUriel Korach2017-09-101-10/+0
| | | | llvm-svn: 312879
* [X86] Don't disable slow INC/DEC if optimizing for sizeCraig Topper2017-09-094-11/+18
| | | | | | | | | | | | | | | | | Summary: Just because INC/DEC is a little slow on some processors doesn't mean we shouldn't prefer it when optimizing for size. This appears to match gcc behavior. Reviewers: chandlerc, zvi, RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37177 llvm-svn: 312866
* [DivRempairs] add a pass to optimize div/rem pairs (PR31028)Sanjay Patel2017-09-092-0/+6
| | | | | | | | | | | | | | | | | | This is intended to be a superset of the functionality from D31037 (EarlyCSE) but implemented as an independent pass, so there's no stretching of scope and feature creep for an existing pass. I also proposed a weaker version of this for SimplifyCFG in D30910. And I initially had almost this same functionality as an addition to CGP in the motivating example of PR31028: https://bugs.llvm.org/show_bug.cgi?id=31028 The advantage of positioning this ahead of SimplifyCFG in the pass pipeline is that it can allow more flattening. But it needs to be after passes (InstCombine) that could sink a div/rem and undo the hoisting that is done here. Decomposing remainder may allow removing some code from the backend (PPC and possibly others). Differential Revision: https://reviews.llvm.org/D37121 llvm-svn: 312862
* [X86] Call removeDeadNode when we're done doing custom isel for mul, div and ↵Craig Topper2017-09-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | test Summary: Once we've done our custom isel for these nodes, I think we should be calling removeDeadNode to prune them out of the DAG. Table driven isel ultimately either calls morphNodeTo which modifies a node and doesn't leave dead nodes. Or it emits new nodes and then calls removeDeadNode as part of Opc_CompleteMatch. If you run a simple multiply test case like this through llc with -debug you'll see a umul_lohi node get printed as part of the dump for Instruction Selection ends. ``` define i64 @foo(i64 %a, i64 %b) local_unnamed_addr #0 { entry: %conv = zext i64 %a to i128 %conv1 = zext i64 %b to i128 %mul = mul nuw nsw i128 %conv1, %conv %shr = lshr i128 %mul, 64 %conv2 = trunc i128 %shr to i64 ret i64 %conv2 } ``` Reviewers: RKSimon, spatel, zvi, guyblank, niravd Reviewed By: niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37547 llvm-svn: 312857
* [X86] Use ReplaceNode instead of ReplaceUses when converting ↵Craig Topper2017-09-091-1/+1
| | | | | | | | X86ISD::SHRUNKBLEND to ISD::VSELECT during isel. This ensures that the SHRUNKBLEND node gets erased immediately. llvm-svn: 312856
* PPC: Don't select lxv/stxv for insufficiently aligned stack slots.Kyle Butt2017-09-091-1/+11
| | | | | | | | | | | | | | The lxv/stxv instructions require an offset that is 0 % 16. Previously we were selecting lxv/stxv for loads and stores to the stack where the offset from the slot was a multiple of 16, but the stack slot was not 16 or more byte aligned. When the frame gets lowered these transform to r(1|31) + slot + offset. If slot is not aligned, slot + offset may not be 0 % 16. Now we require 16 byte or more alignment for select lxv/stxv to stack slots. Includes a testcase that shows both sufficiently and insufficiently aligned stack slots. llvm-svn: 312843
* [AMDGPU] Remove unused function. NFCI.Davide Italiano2017-09-081-9/+0
| | | | llvm-svn: 312836
* bpf: proper print imm64 expression in inst printerYonghong Song2017-09-082-2/+4
| | | | | | | | | | | | | | Fixed an issue in printImm64Operand where if the value is an expression, print out the expression properly. Currently, it will print r1 = <MCOperand Expr:(tx_port)>ll With the patch, the printout will be r1 = tx_port Suggested-by: Jiong Wang <jiong.wang@netronome.com> Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 312833
* AMDGPU: Start using !con operatorMatt Arsenault2017-09-081-14/+12
| | | | | | | | | | | | | We have a lot of operand definition work essentially producing every valid permutation of operands to workaround builiding operand lists based on the instruction features. Apparently tablegen already has a mostly undocumented operator to concat dags which simplies this. Convert one simple place to use this. The BUF instruction definitions have much more complicated logic that can be totally rewritten now. llvm-svn: 312822
* AMDGPU: Recompute scc livenessMatt Arsenault2017-09-081-1/+7
| | | | | | | | The various scalar bit operations set SCC, so one is erased or moved it needs to be recomputed. Not sure why the existing tests don't fail on this. llvm-svn: 312819
* [x86] Fix GCC pedantic warnings about default arguments for lambdas.Chandler Carruth2017-09-081-6/+6
| | | | llvm-svn: 312809
* [SLP] Support for horizontal min/max reduction.Alexey Bataev2017-09-082-0/+149
| | | | | | | | | | | | | SLP vectorizer supports horizontal reductions for Add/FAdd binary operations. Patch adds support for horizontal min/max reductions. Function getReductionCost() is split to getArithmeticReductionCost() for binary operation reductions and getMinMaxReductionCost() for min/max reductions. Patch fixes PR26956. Differential revision: https://reviews.llvm.org/D27846 llvm-svn: 312791
* [XRay][CodeGen][PowerPC] Fix tail exit codegen for XRay in PPCDean Michael Berris2017-09-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This fixes code-gen for XRay in PPC. The regression wasn't caught by codegen tests which we add in this change. What happened was the following: - For tail exits, we used to unconditionally prepend the returns/exits with a pseudo-instruction that gets lowered to the instrumentation sled (and leave the actual return/exit instruction as-is). - Changes to the XRay instrumentation pass caused the tail exits to suddenly also emit the tail exit pseudo-instruction, since the check for whether a return instruction was also a call instruction meant it was a tail exit instruction. - None of the tests caught the regression either due to non-existent tests, or the tests being disabled/removed for continuous breakage. This change re-introduces some of the basic tests and verifies that we're back to a state that allows the back-end to generate appropriate XRay instrumented binaries for PPC in the presence of tail exits. Reviewers: echristo, timshen Subscribers: nemanjai, kbarton, llvm-commits Differential Revision: https://reviews.llvm.org/D37570 llvm-svn: 312772
* [x86] Flesh out the custom ISel for RMW aritmetic ops with used flags toChandler Carruth2017-09-081-2/+32
| | | | | | | | | | | | | | | | cover the bitwise operators. Nothing really exciting here, this just stamps out the rest of the core operations that can RMW memory and set flags. Still not implemented here: ADC, SBB. Those will require more interesting logic to channel the flags *in*, and I'm not currently planning to try to tackle that. It might be interesting for someone who wants to improve our code generation for bignum implementations. Differential Revision: https://reviews.llvm.org/D37141 llvm-svn: 312768
* [x86] Extend the manual ISel of `add` and `sub` with both RMW memoryChandler Carruth2017-09-071-15/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | operands and used flags to support matching immediate operands. This is a bit trickier than register operands, and we still want to fall back on a register operands even for things that appear to be "immediates" when they won't actually select into the operation's immediate operand. This also requires us to handle things like selecting `sub` vs. `add` to minimize the number of bits needed to represent the immediate, and picking the shortest immediate encoding. In order to that, we in turn need to scan to make sure that CF isn't used as it will get inverted. The end result seems very nice though, and we're now generating optimal instruction sequences for these patterns IMO. A follow-up patch will further expand this to other operations with RMW memory operands. But handing `add` and `sub` are useful starting points to flesh out the machinery and make sure interesting and complex cases can be handled. Thanks to Craig Topper who provided a few fixes and improvements to this patch in addition to the review! Differential Revision: https://reviews.llvm.org/D37139 llvm-svn: 312764
* Sink some IntrinsicInst.h and Intrinsics.h out of llvm/includeReid Kleckner2017-09-072-0/+2
| | | | | | | Many of these uses can get by with forward declarations. Hopefully this speeds up compilation after adding a single intrinsic. llvm-svn: 312759
* [CUDA] Added rudimentary support for CUDA-9 and sm_70.Artem Belevich2017-09-071-0/+5
| | | | | | | | | | | | | For now CUDA-9 is not included in the list of CUDA versions clang searches for, so the path to CUDA-9 must be explicitly passed via --cuda-path=. On LLVM side NVPTX added sm_70 GPU type which bumps required PTX version to 6.0, but otherwise is equivalent to sm_62 at the moment. Differential Revision: https://reviews.llvm.org/D37576 llvm-svn: 312734
* AMDGPU: Start selecting v_mad_mix_f32Matt Arsenault2017-09-074-5/+105
| | | | llvm-svn: 312732
* AMDGPU: Handle non-temporal loads and storesKonstantin Zhuravlyov2017-09-071-23/+59
| | | | | | Differential Revision: https://reviews.llvm.org/D36862 llvm-svn: 312729
* AMDGPU: Handle more than one memory operand in SIMemoryLegalizerKonstantin Zhuravlyov2017-09-072-58/+145
| | | | | | Differential Revision: https://reviews.llvm.org/D37397 llvm-svn: 312725
* [ARM] Remove redundant vcvt patterns.Benjamin Kramer2017-09-071-14/+0
| | | | | | | | These don't add any value as they're just compositions of existing patterns. However, they can confuse the cost logic in ISel, leading to duplicated vcvt instructions like in PR33199. llvm-svn: 312724
* [X86][LLVM]Expanding Supports lowerInterleavedLoad() in X86InterleavedAccess ↵Michael Zuckerman2017-09-071-20/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (VF{8|16|32} stride 3). This patch expands the support of lowerInterleavedload to {8|16|32}x8i stride 3. LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=3 VF={8|16|32}) and we plan to include the store (deinterleved side). The patch goal is to optimize the following sequence: a0 b0 c0 a1 b1 c1 a2 b2 c2 a3 b3 c3 a4 b4 c4 a5 b5 c5 a6 b6 c6 a7 b7 c7 into a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 Reviewers 1. zvi 2. igor 3. guyblank 4. dorit 5. Ayal llvm-svn: 312722
* [mips] Use RegisterMCAsmBackend to register all MIPS asm backends. NFCSimon Atanasyan2017-09-075-81/+28
| | | | | | | | | | | | | This change converts the `MipsAsmBackend` constructor to the "standard" form. It makes possible to use `RegisterMCAsmBackend` for the backends registrations. Now we pass `Triple` instance to the `MipsAsmBackend` ctor and deduce all required options like endianness and bitness from the triple. We still need to implement explicit ABI checking for providing correct options to backends. Differential revision: https://reviews.llvm.org/D37519 llvm-svn: 312720
* [Sparc][NFC] Clean up SelectCC loweringAlex Bradbury2017-09-071-44/+40
| | | | | | | | | | | | | | The ARM, BPF, MSP430, Sparc and Mips backends all use a similar code sequence for lowering SelectCC. As pointed out by @reames in D29937, this code isn't particularly clear and in most of these backends doesn't actually match the comments. This patch makes the code sequence clearer for the Sparc backend through better variable naming and more accurate comments (e.g. we are inserting triangle control flow, _not_ diamond). There is no functional change. Differential Revision: https://reviews.llvm.org/D37194 llvm-svn: 312713
* X86: Improve AVX512 fptoui loweringZvi Rackover2017-09-073-0/+11
| | | | | | | | | | | | | | | | | Summary: Add patterns for fptoui <16 x float> to <16 x i8> fptoui <16 x float> to <16 x i16> Reviewers: igorb, delena, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37505 llvm-svn: 312704
* [X86] Force shuffle lowering to only create X86ISD::VPERM2X128 with 64-bit ↵Craig Topper2017-09-072-22/+5
| | | | | | | | | | element types so we can remove some patterns from isel. Intrinsic handling is still creating these nodes with 32-bit elements as well. But at least this gets rid of 8 and 16. Ideally, someday we'll convert the intrinsics to generic vector shuffles and remove the intrinsics. llvm-svn: 312702
* AMDGPU: Don't legalize i16 extloads to i32 with legal i16Matt Arsenault2017-09-073-1/+8
| | | | | | | Keeping non-i16 extloads makes it easier to match some new gfx9 load instructions. llvm-svn: 312699
* [X86] Remove patterns for selecting a v8f32 X86ISD::MOVSS or v4f64 ↵Craig Topper2017-09-072-48/+0
| | | | | | | | X86ISD::MOVSD. I don't think we ever generate these. If we did, I would expect we would also be able to generate v16f32 and v8f64, but we don't have those patterns. llvm-svn: 312694
* ARM: track globals promoted to coalesced const pool entriesSaleem Abdulrasool2017-09-073-13/+27
| | | | | | | | | | | | | Globals that are promoted to an ARM constant pool may alias with another existing constant pool entry. We need to keep a reference to all globals that were promoted to each constant pool value so that we can emit a distinct label for each promoted global. These labels are necessary so that debug info can refer to the promoted global without an undefined reference during linking. Patch by Stephen Crane! llvm-svn: 312692
* [AMDGPU] Use v_pk_max_f16 for fcanonicalizeStanislav Mekhanoshin2017-09-061-5/+10
| | | | | | Differential Revision: https://reviews.llvm.org/D37325 llvm-svn: 312676
* Insert IMPLICIT_DEFS for undef uses in tail mergingMatthias Braun2017-09-062-24/+20
| | | | | | | | | | | | | | | | | | | | | Tail merging can convert an undef use into a normal one when creating a common tail. Doing so can make the register live out from a block which previously contained the undef use. To keep the liveness up-to-date, insert IMPLICIT_DEFs in such blocks when necessary. To enable this patch the computeLiveIns() function which used to compute live-ins for a block and set them immediately is split into new functions: - computeLiveIns() just computes the live-ins in a LivePhysRegs set. - addLiveIns() applies the live-ins to a block live-in list. - computeAndAddLiveIns() is a convenience function combining the other two functions and behaving like computeLiveIns() before this patch. Based on a patch by Krzysztof Parzyszek <kparzysz@codeaurora.org> Differential Revision: https://reviews.llvm.org/D37034 llvm-svn: 312668
* [X86] Move more isel patterns to X86InstrVecCompiler.td. NFCCraig Topper2017-09-063-437/+184
| | | | | | This moves more of our subvector insert/extract tricks to X86InstrVecCompiler.td and refactors them into multiclasses. llvm-svn: 312661
* [AMDGPU] Fixed encoding of v_pk_mul_f16 in fcanonicalizeStanislav Mekhanoshin2017-09-061-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D37522 llvm-svn: 312660
* [X86] Actually add the new file that was supposed to go with r312649.Craig Topper2017-09-061-0/+179
| | | | llvm-svn: 312650
* [X86] Introduce a new td file to hold patterns some of the non instruction ↵Craig Topper2017-09-063-211/+1
| | | | | | | | | | | | patterns from SSE and AVX512 This patch moves some of similar non-instruction patterns from X86InstrSSE.td and X86InstrAVX512.td to a common file. This is intended as a starting point. There are many other optimization patterns that exist in both files that we could move here. Differential Revision: https://reviews.llvm.org/D37455 llvm-svn: 312649
* [Hexagon] Add option to generate calls to "abort" for "unreachable"Krzysztof Parzyszek2017-09-061-0/+6
| | | | llvm-svn: 312644
* [AMDGPU] Fix shouldClusterMemOps to process flat loadsStanislav Mekhanoshin2017-09-061-0/+4
| | | | | | | | Flat loads do not have vdata operand but have vdst instead. Differential Revision: https://reviews.llvm.org/D37502 llvm-svn: 312640
* AMDGPU: Make worst-case assumption about the wait states in inline assemblyNicolai Haehnle2017-09-061-1/+2
| | | | | | | | | | | | | | | | Summary: Mesa still uses a hack where empty inline assembly is used as a kind of optimization barrier. This exposed a problem where not enough wait states were inserted, because the hazard recognizer implicitly assumed that each inline assembly "instruction" has at least one wait state. Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D37205 llvm-svn: 312635
* [X86][X87] Ensure x87 instructions are tagged as altering the FPSW regSimon Pilgrim2017-09-061-7/+8
| | | | | | | | | | As noted in PR34080, a lot of x87 instructions alter the FPSW status register (or leave it in an undefined state) but aren't tagged as such in the tablegen. This patch tags the control word, stack, wait and math instructions as altering FPSW, which matches what the AMD APMs suggests happens. Differential Revision: https://reviews.llvm.org/D36414 llvm-svn: 312629
* [RISCV][NFC] Fix sorting of includes in lib/Target/RISCVAlex Bradbury2017-09-062-6/+6
| | | | llvm-svn: 312624
* [x86] Fix PR34377 by disabling cmov conversion when we relied on itChandler Carruth2017-09-061-0/+10
| | | | | | | | | | | performing a zext of a register. On the PR there is discussion of how to more effectively handle this, but this patch prevents us from miscompiling code. Differential Revision: https://reviews.llvm.org/D37504 llvm-svn: 312620
* [X86] Add more FMA3 patterns to cover a load in all 3 possible positions.Craig Topper2017-09-062-68/+137
| | | | | | This matches what we already do for AVX512. The peephole pass makes up for this in most if not all cases. But this makes isel behavior for these consistent with every other instruction. llvm-svn: 312613
* [PowerPC] Don't use xscvdpspn on the P7Hal Finkel2017-09-061-3/+6
| | | | | | | xscvdpspn was not introduced until the P8, so don't use it on the P7. Fixes a regression introduced in r288152. llvm-svn: 312612
* [X86] Allow cross-lane permutations for sub targets supporting AVX2.Jatin Bhateja2017-09-061-11/+21
| | | | | | | | | | | | | | Summary: Most instructions in AVX work “in-lane”, that is, each source element is applied only to other elements of the same lane, thus a cross lane permutation is costly and needs more than one instrution. AVX2 includes instructions to perform any-to-any permutation of words over a 256-bit register and vectorized table lookup. This should also Fix PR34369 Differential Revision: https://reviews.llvm.org/D37388 llvm-svn: 312608
* [AMDGPU] Transform __read_pipe_* and __write_pipe_*Yaxun Liu2017-09-063-74/+377
| | | | | | | | | When packet size equals packet align and is power of 2, transform __read_pipe* and __write_pipe* to specialized library function. Differential Revision: https://reviews.llvm.org/D36831 llvm-svn: 312598
* [ARM] Make ARMExpandPseudo add implicit uses for predicated instructionsEli Friedman2017-09-051-8/+26
| | | | | | | | | | | Missing these could potentially screw up post-ra scheduling. Issue found by inspection, so I don't have a real testcase. Included test just verifies the expected operands after expansion. Differential Revision: https://reviews.llvm.org/D35156 llvm-svn: 312589
* [ARM] Register ARMExpandPseudo pass.Eli Friedman2017-09-053-1/+8
| | | | | | | | This allows -run-pass etc. to refer to it. (Split off from D35156.) llvm-svn: 312587
* [X86] Remove unnecessary (v4f32 (X86vzmovl (v4f32 (scalar_to_vector ↵Craig Topper2017-09-052-10/+0
| | | | | | | | | | | | | | | | | | FR32X)))) patterns We had already disabled the pattern for SSE4.1 and SSE4.2. But it got re-enabled for AVX and AVX512. With SSE41 we rely on a separate (v4f32 (X86vzmovl VR128)) pattern to select blendps with a xorps to create zeroess. And a separate (v4f32 (scalar_to_vector FR32X)) to select a COPY_TO_REG_CLASS to move FR32 to VR128 The same thing can happen for AVX with vblendps and those separate patterns already exist. For AVX512, (v4f32 (X86vzmov VR128)) will select a VMOVSS instruction instead of VBLENDPS due to their not being a EVEX VBLENDPS. This is what we were getting out of the larger pattern anyway. So the larger pattern is unneeded for AVX512 too. For SSE1-SSSE3 we can rely on (v4f32 (X86vzmov VR128)) selecting a MOVSS similar to AVX512. Again this is what the larger pattern did too. So the only real change here is that AVX1/2 now properly outputs a VBLENDPS during isel instead of a VMOVSS to match SSE41. Most tests didn't notice because the two address instruction pass knows how to turn VMOVSS into VBLENDPS to get an independent destination register. llvm-svn: 312564
* AMDGPU: Cleanup/refactor SIMemoryLegalizer [3]:Konstantin Zhuravlyov2017-09-051-143/+157
| | | | | | | | | - Refactor SIMemOpInfo's constructors - Allow construction of NotAtomic SIMemOpInfo Differential Revision: https://reviews.llvm.org/D37396 llvm-svn: 312563
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