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* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-1/+2
| | | | llvm-svn: 134606
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134281
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-2/+2
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-1/+4
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-301-3/+3
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Remove TargetOptions.h dependency from X86Subtarget.Evan Cheng2011-06-231-4/+2
| | | | llvm-svn: 133726
* ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()Daniel Dunbar2011-04-191-3/+7
| | | | | | predicates. llvm-svn: 129816
* Target/X86: Eliminate uses of getDarwinVers().Daniel Dunbar2011-04-191-7/+0
| | | | llvm-svn: 129813
* Target/X86: Add getTargetTriple() accessor.Daniel Dunbar2011-04-191-0/+2
| | | | llvm-svn: 129812
* Stack alignment is 16 bytes on FreeBSD/i386 too.Roman Divacky2011-02-221-0/+1
| | | | llvm-svn: 126226
* The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri.Duncan Sands2011-02-211-0/+1
| | | | llvm-svn: 126130
* Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.NAKAMURA Takumi2011-02-171-3/+1
| | | | | | No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way. llvm-svn: 125747
* Fix whitespace.NAKAMURA Takumi2011-02-171-5/+5
| | | | llvm-svn: 125746
* Patches to build EFI with Clang/LLVM. By Carl Norum.Evan Cheng2011-02-011-0/+4
| | | | llvm-svn: 124639
* Formalize the notion that AVX and SSE are non-overlapping extensions from ↵Nate Begeman2010-12-101-0/+2
| | | | | | the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
* Add patterns for the x86 popcnt instruction.Benjamin Kramer2010-12-041-0/+4
| | | | | | | - Also adds a new POPCNT subtarget feature that is currently enabled if the target supports SSE4.2 (nehalem) or SSE4A (barcelona). llvm-svn: 120917
* Jim Asked us to move DataLayout on ARM back to the most specialized classes. DoRafael Espindola2010-10-031-14/+0
| | | | | | | | so and also change X86 for consistency. Investigating if this can be improved a bit. llvm-svn: 115469
* X86Subtarget.h: Fix Cygwin's TD.NAKAMURA Takumi2010-09-181-1/+1
| | | | llvm-svn: 114297
* Properly emit __chkstk call instead of __alloca on non-mingw windows targets.Anton Korobeynikov2010-09-021-0/+4
| | | | | | Patch by Cameron Esfahani! llvm-svn: 112902
* Add x86 CLMUL (Carry-less multiplication) cpu featureBruno Cardoso Lopes2010-07-231-0/+4
| | | | llvm-svn: 109206
* Have the X86 backend use Triple instead of a string and some enums.Eric Christopher2010-07-051-18/+25
| | | | llvm-svn: 107625
* FastISel doesn't yet handle callee-pop functions.Dan Gohman2010-05-271-0/+4
| | | | | | To support this, move IsCalleePop from X86ISelLowering to X86Subtarget. llvm-svn: 104866
* Enable i16 to i32 promotion by default.Evan Cheng2010-04-281-5/+0
| | | | llvm-svn: 102493
* isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.Evan Cheng2010-04-211-2/+6
| | | | llvm-svn: 101979
* Separate out the AES-NI instructions from the SSE4.2 instructions. AddEric Christopher2010-04-021-0/+4
| | | | | | | | | a new subtarget option for AES and check for the support. Add "westmere" line of processors and add AES-NI support to the core i7. Add a couple of TODOs for information I couldn't verify. llvm-svn: 100231
* Nehalem unaligned memory access is fast.Evan Cheng2010-04-011-0/+4
| | | | llvm-svn: 100089
* Turning off post-ra scheduling for x86. It isn't a consistent win.Evan Cheng2010-03-181-6/+0
| | | | llvm-svn: 98810
* add support for pentium class CPUs which do not have cmov,Chris Lattner2010-03-141-0/+1
| | | | | | PR4841. Patch by Craig Smith! llvm-svn: 98496
* 80-col violations/trailing whitespace.Mikhail Glushenkov2010-02-281-11/+12
| | | | llvm-svn: 97427
* Setup correct data layout to match gcc's expectations on mingw32.Anton Korobeynikov2010-02-121-1/+1
| | | | llvm-svn: 95981
* Fix typo.Duncan Sands2010-01-121-1/+1
| | | | llvm-svn: 93235
* Tweak commit 91745, which changed target data for both Mingw and Cygwin,Duncan Sands2010-01-121-1/+1
| | | | | | | to not touch Cygwin: the change caused llvm-gcc build failures due to long double getting the wrong size. Patch by Aaron Gray. llvm-svn: 93234
* Implement a feature (-vector-unaligned-mem) to allow targets toDavid Greene2010-01-111-0/+5
| | | | | | | | ignore alignment requirements for SIMD memory operands. This is useful on architectures like the AMD 10h that do not trap on unaligned references if a status bit is twiddled at startup time. llvm-svn: 93151
* Remove target attribute break-sse-dep. Instead, do not fold load into sse ↵Evan Cheng2009-12-221-9/+0
| | | | | | partial update instructions unless optimizing for size. llvm-svn: 91910
* Bump alignment requirements for windows targets to achieve compartibility ↵Anton Korobeynikov2009-12-191-0/+3
| | | | | | | | with vcpp. Based on patch by Michael Beck! llvm-svn: 91745
* On recent Intel u-arch's, folding loads into some unary SSE instructions canEvan Cheng2009-12-181-0/+9
| | | | | | | | | | | | | | | | | | | be non-optimal. To be precise, we should avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g. movss (%rdi), %xmm0 cvtss2sd %xmm0, %xmm0 instead of cvtss2sd (%rdi), %xmm0 An alternative method to break dependency is to clear the register first. e.g. xorps %xmm0, %xmm0 cvtss2sd (%rdi), %xmm0 llvm-svn: 91672
* Target-independent support for TargetFlags on BlockAddress operands,Dan Gohman2009-11-201-0/+5
| | | | | | and support for blockaddresses in x86-32 PIC mode. llvm-svn: 89506
* Allow target to specify regclass for which antideps will only be broken ↵David Goodwin2009-11-131-1/+1
| | | | | | along the critical path. llvm-svn: 88682
* Fixed to address code review. No functional changes.David Goodwin2009-11-101-5/+1
| | | | llvm-svn: 86634
* Allow targets to specify register classes whose member registers should not ↵David Goodwin2009-11-101-2/+4
| | | | | | be renamed to break anti-dependencies. llvm-svn: 86628
* indicate what the native integer types for the target are.Chris Lattner2009-11-071-3/+3
| | | | | | Please verify. llvm-svn: 86397
* X86 needs critical path anti-dependency breaking.Evan Cheng2009-10-231-1/+1
| | | | llvm-svn: 84931
* Allow the target to select the level of anti-dependence breaking that should ↵David Goodwin2009-10-221-1/+3
| | | | | | be performed by the post-RA scheduler. The default is none. llvm-svn: 84911
* Turn on post-alloc scheduling for x86.Evan Cheng2009-10-181-2/+1
| | | | llvm-svn: 84431
* Oops. I forgot to change the tests first. Disable post-alloc scheduling.Evan Cheng2009-10-181-1/+1
| | | | llvm-svn: 84425
* -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixedEvan Cheng2009-10-181-1/+1
| | | | | | | | | | | stack slots and giving them different PseudoSourceValue's did not fix the problem of post-alloc scheduling miscompiling llvm itself. - Apply Dan's conservative workaround by assuming any non fixed stack slots can alias other memory locations. This means a load from spill slot #1 cannot move above a store of spill slot #2. - Enable post-alloc scheduling for x86 at optimization leverl Default and above. llvm-svn: 84424
* Change createPostRAScheduler so it can be turned off at llc -O1.Evan Cheng2009-10-161-0/+7
| | | | llvm-svn: 84273
* Remove X86Subtarget::IsLinux. It's no longer being used.Evan Cheng2009-10-151-8/+1
| | | | llvm-svn: 84200
* rearrange X86ATTAsmPrinter::doFinalization, making a scan of Chris Lattner2009-09-161-1/+9
| | | | | | the global variable list only happen for COFF targets. llvm-svn: 82010
* Make these functions static and local.Daniel Dunbar2009-09-031-8/+0
| | | | llvm-svn: 80892
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