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* [X86] Split off F16C WriteCvtPH2PS/WriteCvtPS2PH scheduler classesSimon Pilgrim2018-05-151-19/+10
| | | | | | | | | Btver2 - VCVTPH2PSYrm needs to double pump the AGU Broadwell - missing VCVTPS2PH*mr stores extra latency Allows us to remove the WriteCvtF2FSt conversion store class llvm-svn: 332357
* [X86] Add NT load/store scheduler classesSimon Pilgrim2018-05-141-5/+11
| | | | llvm-svn: 332274
* [X86] Add WriteFCMOV scheduler class for x87 CMOVsSimon Pilgrim2018-05-121-2/+2
| | | | llvm-svn: 332173
* [X86][MMX] Tag MMX Move/Load/Store as WriteVec schedule classesSimon Pilgrim2018-05-111-3/+0
| | | | | | Fixes an issue on SLM/Btver2 where we had instructions were being treated as scalar loads/stores llvm-svn: 332104
* [X86] Split WriteF/WriteVec Move/Load/Store scheduler classes by vector widthSimon Pilgrim2018-05-111-10/+14
| | | | | | Fixes a SNB issue that was missing vlddqu/vmovntdqa ymm instructions llvm-svn: 332094
* [X86] Convert/Merge more instregex patterns to reduce InstrRW compile time.Simon Pilgrim2018-05-101-47/+30
| | | | | | Use instrs lists or merge multiple instregex patterns. llvm-svn: 332022
* [X86] Split ↵Simon Pilgrim2018-05-101-70/+20
| | | | | | | | WriteVecALU/WriteVecLogic/WriteShuffle/WriteVarShuffle/WritePSADBW/WritePHAdd scheduler classes Split off XMM classes from the default (MMX) classes. llvm-svn: 331999
* [X86] Merge instregex patterns to reduce InstrRW compile time.Simon Pilgrim2018-05-091-90/+37
| | | | llvm-svn: 331911
* [X86] Cleanup WriteFStore/WriteVecStore schedulesSimon Pilgrim2018-05-091-13/+2
| | | | | | | | MOVNTPD/MOVNTPS should be WriteFStore Standardized BDW/HSW/SKL/SKX WriteFStore/WriteVecStore - fixes some missed instregex patterns. (V)MASKMOVDQU was already using the default, its costs gets increased but is still nowhere near the real cost of that nasty instruction.... llvm-svn: 331864
* [X86] Split off WriteIMul64 from WriteIMul schedule class (PR36931)Simon Pilgrim2018-05-081-2/+3
| | | | | | | This fixes a couple of BtVer2 missing instructions that weren't been handled in the override. NOTE: There are still a lot of overrides that still need cleaning up! llvm-svn: 331770
* [X86] Split WriteIDiv into div/idiv 8/16/32/64 implementations (PR36930)Simon Pilgrim2018-05-081-1/+10
| | | | | | | I've created the necessary classes but there are still a lot of overrides that need cleaning up. NOTE: The Znver1 model was missing some div/idiv variants in the instregex patterns and wasn't setting the resource cycles at all in the overrides. llvm-svn: 331767
* [X86] Add vector masked load/store scheduler classes (PR32857)Simon Pilgrim2018-05-081-26/+16
| | | | | | Split off from existing vector load/store classes to remove InstRW overrides. llvm-svn: 331760
* [X86] Add SchedWriteFTest/SchedWriteVecTest TEST scheduler classesSimon Pilgrim2018-05-081-30/+7
| | | | | | Split off from SchedWriteVecLogic to remove InstRW overrides. llvm-svn: 331757
* [X86] Split WriteFAdd/WriteFCmp/WriteFMul schedule classesSimon Pilgrim2018-05-071-25/+22
| | | | | | | | Split to support single/double for scalar, XMM and YMM/ZMM instructions - removing InstrRW overrides for these instructions. Fixes Atom ADDSUBPD instruction and reclassifies VFPCLASS as WriteFCmp which is closer in behaviour. llvm-svn: 331672
* [X86][AVX2] Tag VPMOVSX/VPMOVZX ymm instructions as WriteShuffle256Simon Pilgrim2018-05-071-19/+2
| | | | | | | | These are more like cross-lane shuffles than regular shuffles - we already do this for AVX512 equivalents. Differential Revision: https://reviews.llvm.org/D46229 llvm-svn: 331659
* [X86] Split WriteFDiv schedule classes to support single/double scalar, XMM ↵Simon Pilgrim2018-05-071-32/+17
| | | | | | | | and YMM/ZMM instructions. This removes all InstrRW overrides for these instructions - some x87 overrides remain but most use default (and realistic) values. llvm-svn: 331643
* [X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt schedule classesSimon Pilgrim2018-05-071-87/+18
| | | | | | | | | | | | | WriteFRcp/WriteFRsqrt are split to support scalar, XMM and YMM/ZMM instructions. WriteFSqrt is split into single/double/long-double sizes and scalar, XMM, YMM and ZMM instructions. This removes all InstrRW overrides for these instructions. NOTE: There were a couple of typos in the Znver1 model - notably a 1cy throughput for SQRT that is highly unlikely and doesn't tally with Agner. NOTE: I had to add Agner's numbers for several targets for WriteFSqrt80. llvm-svn: 331629
* [X86] Add WriteEMMS scheduler classSimon Pilgrim2018-05-041-7/+1
| | | | | | Filled in the missing values from Btver2 SoG or Agner llvm-svn: 331546
* [X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW ↵Simon Pilgrim2018-05-041-33/+8
| | | | | | overrides. llvm-svn: 331543
* [X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWidths directly.Simon Pilgrim2018-05-041-2/+2
| | | | | | Rename scalar and XMM versions, this is to match/simplify an upcoming change to split MUL/DIV/SQRT scalar/xmm/ymm/zmm classes. llvm-svn: 331531
* [X86] Add WriteVecMOVMSKY scheduler classSimon Pilgrim2018-05-041-3/+4
| | | | llvm-svn: 331525
* [X86] Add SchedWriteFRnd fp rounding scheduler classesSimon Pilgrim2018-05-041-28/+2
| | | | | | | | Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions. Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA. llvm-svn: 331515
* [X86] Add WriteDPPD/WriteDPPS dot product scheduler classesSimon Pilgrim2018-05-031-35/+3
| | | | llvm-svn: 331489
* [X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM ↵Simon Pilgrim2018-05-031-73/+11
| | | | | | | | scheduler classes This took a bit of extra work as on Intel targets the old (V)PSLLDrr/(V)PSLLDrm style instructions act differently - I ended up creating WriteVecShiftImm classes for XMM/YMM/ZMM vector shift by immediate and retaining WriteVecShift as the default (used only by MMX) plus WriteVecShiftX/WriteVecShiftY. X86SchedWriteWidths hides most of this thank goodness. llvm-svn: 331472
* [X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-031-143/+10
| | | | llvm-svn: 331453
* [X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and ↵Simon Pilgrim2018-05-031-43/+14
| | | | | | | | YMM/ZMM scheduler classes Also retagged VDBPSADBW instructions as SchedWritePSADBW instead of SchedWriteVecIMul which matches the behaviour on SkylakeServer (the only thing that supports it...) llvm-svn: 331445
* [X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM ↵Simon Pilgrim2018-05-021-21/+13
| | | | | | and YMM/ZMM scheduler classes llvm-svn: 331386
* [X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler ↵Simon Pilgrim2018-05-021-30/+12
| | | | | | classes with more common default values llvm-svn: 331380
* [X86] Cleanup WriteFMul scheduler classes with more common default valuesSimon Pilgrim2018-05-021-10/+2
| | | | | | Intel models were targeting x87 instead of packed sse. llvm-svn: 331360
* [X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default ↵Simon Pilgrim2018-05-021-31/+10
| | | | | | | | | | values Intel models were targeting x87 instead of packed sse. Also fixes XOP's VFRCZ to use WriteFAdd/WriteFAddY. llvm-svn: 331340
* [X86] Split WriteFMul/WriteFDiv into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-011-7/+9
| | | | llvm-svn: 331293
* [X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt into XMM and YMM/ZMM scheduler ↵Simon Pilgrim2018-05-011-3/+6
| | | | | | classes llvm-svn: 331290
* [X86] Split WriteFCmp into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-011-6/+1
| | | | | | Removes more WriteFCmp InstRW overrides llvm-svn: 331283
* [X86] Split WriteFAdd into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-011-1/+2
| | | | | | Removes more WriteFAdd InstRW overrides llvm-svn: 331276
* [X86] Split WriteFShuffle into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-011-10/+3
| | | | | | Removes more WriteFShuffle InstRW overrides llvm-svn: 331264
* [X86] Split WriteVecLogic into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-011-5/+2
| | | | | | This removes all the WriteVecLogic InstRW overrides. llvm-svn: 331258
* [X86] Tag PSLLDQ/PSRLDQ as WriteShuffle scheduler classes instead of shifts.Simon Pilgrim2018-05-011-3/+1
| | | | | | Although they are encoded similar to bit shifts, the byte shifts behave like shuffles from a scheduling point of view. llvm-svn: 331253
* [X86] Merge more instregex single matches to reduce InstrRW compile time.Simon Pilgrim2018-04-291-3/+2
| | | | llvm-svn: 331143
* [X86] Remove SLDT64m instruction.Craig Topper2018-04-291-1/+0
| | | | | | | | It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything. While I was touching the encoding tests to remove it, I added some other missing register form test cases. llvm-svn: 331135
* [X86] Remove unnecessary shift/rotate folded InstRW overrides.Simon Pilgrim2018-04-281-7/+1
| | | | llvm-svn: 331110
* [X86] Merge some x87 instruction instregex single matches. NFCI.Simon Pilgrim2018-04-271-50/+16
| | | | llvm-svn: 331084
* [X86] Split WriteFBlend/WriteFVarBlend/WriteFVarShuffle into XMM and YMM/ZMM ↵Simon Pilgrim2018-04-271-11/+4
| | | | | | | | scheduler classes This removes all the WriteFBlend/WriteFVarBlend InstRW overrides - some WriteFVarShuffle remain to be fixed. llvm-svn: 331065
* [X86] Split WriteFHadd into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-04-271-11/+2
| | | | | | This removes all the HADD/HSUB PS/PD InstRW overrides. llvm-svn: 331054
* [X86][AVX] Split WriteFLogic into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-04-271-11/+4
| | | | | | This removes all the AND/ANDN/OR/XOR PS/PD InstRW overrides. llvm-svn: 331051
* [X86] Replace some system instruction instregex single matches with instrs ↵Simon Pilgrim2018-04-271-16/+11
| | | | | | entry. NFCI. llvm-svn: 331034
* [X86] Split WriteFMA into XMM, Scalar and YMM/ZMM scheduler classesSimon Pilgrim2018-04-251-5/+3
| | | | | | | | This removes all the FMA InstRW overrides. If we ever get PR36924, then we can remove many of these declarations from models. llvm-svn: 330820
* [X86] Split off PHMINPOSUW to their own schedule classSimon Pilgrim2018-04-241-2/+1
| | | | | | This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default. llvm-svn: 330756
* [X86][F16C] Add WriteCvtF2FSt scheduling classSimon Pilgrim2018-04-241-7/+6
| | | | | | Fixes the classification of VCVTPS2PHmr/VCVTPS2PHYmr which were tagged as WriteCvtF2FLd_WriteRMW (PR36887) llvm-svn: 330737
* [X86] Remove unnecessary FMA reg-mem InstRW scheduler overrides.Simon Pilgrim2018-04-241-2/+0
| | | | llvm-svn: 330720
* [X86] Add vector element insertion/extraction scheduler classesSimon Pilgrim2018-04-241-24/+22
| | | | | | | | | | | | Split off pinsr/pextr and extractps instructions. (Mostly) fixes PR36887. Note: It might be worth adding a WriteFInsertLd class as well in the future. Differential Revision: https://reviews.llvm.org/D45929 llvm-svn: 330714
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