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* Get rid of one getStackAlignment(). RegisterInfo shouldn't need to know ↵Evan Cheng2011-06-231-3/+4
| | | | | | about stack alignment. llvm-svn: 133679
* SI, DI, BP, and SP don't have 8-bit sub-registers in x86 mode.Jakob Stoklund Olesen2011-06-171-2/+9
| | | | llvm-svn: 133308
* Remove custom allocation order boilerplate that is no longer needed.Jakob Stoklund Olesen2011-06-091-0/+19
| | | | | | | | | | | | | | | | | | | | The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. llvm-svn: 132781
* Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen2011-06-021-2/+1
| | | | | | No functional change. llvm-svn: 132455
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-301-10/+21
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
* Add a GR32_NOREX_NOSP register class and fix a bug where ↵Cameron Zwarich2011-05-271-1/+8
| | | | | | | | | getMatchingSuperRegClass() was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032. llvm-svn: 132225
* Add a method to TargetRegisterInfo to get the register number that the Win64 EHCharles Davis2011-05-241-0/+21
| | | | | | | scheme uses internally. Implement it for x86 (the only architecture that LLVM supports for which this matters right now). llvm-svn: 131969
* Reserve the segment registers on x86 to fix verifier failures in any code thatCameron Zwarich2011-05-181-0/+9
| | | | | | uses them. llvm-svn: 131591
* Fix X86RegisterInfo::getMatchingSuperRegClass for sub_8bit_hi.Jakob Stoklund Olesen2011-05-041-13/+8
| | | | | | | It is OK for B to be any GR8_ABCD_H superclass, the returned register class doesn't have to map surjectively onto B. llvm-svn: 130892
* Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on ↵Jakob Stoklund Olesen2011-04-261-0/+27
| | | | | | | | | | | | register class inflation. The hook will be used by the register allocator when recomputing register classes after removing constraints. Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure that the spill size doesn't change. llvm-svn: 130228
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Re-commit 127368 and 127371. They are exonerated.Evan Cheng2011-03-101-1/+1
| | | | llvm-svn: 127380
* Revert 127368 and 127371 for now.Evan Cheng2011-03-091-1/+1
| | | | llvm-svn: 127376
* Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng2011-03-091-1/+1
| | | | | | | | | | | | | flexible. If it returns a register class that's different from the input, then that's the register class used for cross-register class copies. If it returns a register class that's the same as the input, then no cross- register class copies are needed (normal copies would do). If it returns null, then it's not at all possible to copy registers of the specified register class. llvm-svn: 127368
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-071-0/+20
| | | | llvm-svn: 127175
* Target/X86: Tweak win64's tailcall.NAKAMURA Takumi2011-01-261-0/+6
| | | | llvm-svn: 124272
* lib/Target/X86/X86RegisterInfo.cpp: Fix whitespace.NAKAMURA Takumi2011-01-261-3/+3
| | | | llvm-svn: 124268
* lib/Target/X86/X86RegisterInfo.cpp: Fix a typo in comment.NAKAMURA Takumi2011-01-261-1/+1
| | | | llvm-svn: 124267
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-7/+7
| | | | | | and fixes here and there. llvm-svn: 123170
* Fix the last virtual register enumerations.Jakob Stoklund Olesen2011-01-081-4/+4
| | | | llvm-svn: 123102
* Code clean up. No functionality change.Evan Cheng2010-12-231-49/+48
| | | | llvm-svn: 122528
* Move more PEI-related hooks to TFIAnton Korobeynikov2010-11-271-40/+0
| | | | llvm-svn: 120229
* Move some more hooks to TargetFrameInfoAnton Korobeynikov2010-11-201-36/+1
| | | | llvm-svn: 119904
* Move getInitialFrameState() to TargetFrameInfoAnton Korobeynikov2010-11-181-16/+0
| | | | llvm-svn: 119754
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-30/+19
| | | | llvm-svn: 119740
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov2010-11-151-660/+1
| | | | | | out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place llvm-svn: 119097
* Fix obvious mistake pointed out by Michael Spencer.Jakob Stoklund Olesen2010-10-071-1/+1
| | | | llvm-svn: 115952
* Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.Jakob Stoklund Olesen2010-10-061-1/+6
| | | | | | This function looks like it is about ready to be generated by TebleGen. llvm-svn: 115876
* Properly emit stack probe on win64 (for non-mingw targets).Anton Korobeynikov2010-10-031-31/+47
| | | | | | Based on the patch by Cameron Esfahani! llvm-svn: 115479
* Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.Cameron Esfahani2010-09-221-2/+3
| | | | llvm-svn: 114597
* fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"Chris Lattner2010-09-221-40/+15
| | | | | | Teaching the code generator about CR8-15, how to rex them up, etc. llvm-svn: 114533
* Properly emit __chkstk call instead of __alloca on non-mingw windows targets.Anton Korobeynikov2010-09-021-8/+17
| | | | | | Patch by Cameron Esfahani! llvm-svn: 112902
* Revert win64 changes. They seem to be incompleteAnton Korobeynikov2010-09-021-0/+5
| | | | llvm-svn: 112885
* Properly allocate win64 shadow reg area.Anton Korobeynikov2010-09-021-5/+0
| | | | | | Patch by Jan Sjodin! llvm-svn: 112875
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-261-4/+2
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 llvm-svn: 112241
* Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there.Anton Korobeynikov2010-08-251-2/+4
| | | | | | | | Mark _alloca call as clobberring EFLAGS, otherwise some DCE might remove other flags-clobberring stuff (e.g. cmp instructions) occuring after _alloca call. llvm-svn: 112034
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Add an option to always emit realignment code for a particular module.Eric Christopher2010-08-051-1/+34
| | | | llvm-svn: 110404
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Support x86 "eiz" and "riz" pseudo index registers in the assembler.Bruno Cardoso Lopes2010-07-241-0/+6
| | | | llvm-svn: 109295
* Constify some arguments.Eric Christopher2010-07-201-3/+3
| | | | llvm-svn: 108812
* Remove unnecessary check that was subsumed into canRealignStack.Eric Christopher2010-07-171-3/+2
| | | | llvm-svn: 108588
* Make comment a bit more clear as well as return statement sinceEric Christopher2010-07-171-2/+2
| | | | | | needsStackRealignment is currently checking the can conditions as well. llvm-svn: 108581
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-4/+4
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes2010-07-091-8/+16
| | | | | | | | | | | | | | | notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. llvm-svn: 107996
* Change LEA to have 5 operands for its memory operand, justChris Lattner2010-07-081-2/+2
| | | | | | | | | | | like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-031-3/+2
| | | | | | slots so it's always false. llvm-svn: 107550
* Reapply 105986 with fix for bug pointed out by Jakob:Dale Johannesen2010-06-151-2/+4
| | | | | | | | | flag argument to addReg is not the same format as flags attached to MachineOperand, although both have the same info. I don't think this actually mattered; the bootstrap failure did not reproduce on the next run anyway. llvm-svn: 106049
* Revert 105986; looks like I'd better try bootstrapping.Dale Johannesen2010-06-151-4/+2
| | | | llvm-svn: 105988
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