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authorJakob Stoklund Olesen <stoklund@2pi.dk>2011-06-17 23:15:00 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2011-06-17 23:15:00 +0000
commit157e6a79a1f4ccd9863a4110c09d9b7e5f38f127 (patch)
tree4e37d06bba121f4589dae4cbd46f4d32a5690e84 /llvm/lib/Target/X86/X86RegisterInfo.cpp
parent232431c389c7b1b69cd971b1945a93815c66536a (diff)
downloadbcm5719-llvm-157e6a79a1f4ccd9863a4110c09d9b7e5f38f127.tar.gz
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SI, DI, BP, and SP don't have 8-bit sub-registers in x86 mode.
llvm-svn: 133308
Diffstat (limited to 'llvm/lib/Target/X86/X86RegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/X86/X86RegisterInfo.cpp11
1 files changed, 9 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 1ad6203af2f..9b013a323d8 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -517,13 +517,20 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
// Reserve the registers that only exist in 64-bit mode.
if (!Is64Bit) {
+ // These 8-bit registers are part of the x86-64 extension even though their
+ // super-registers are old 32-bits.
+ Reserved.set(X86::SIL);
+ Reserved.set(X86::DIL);
+ Reserved.set(X86::BPL);
+ Reserved.set(X86::SPL);
+
for (unsigned n = 0; n != 8; ++n) {
+ // R8, R9, ...
const unsigned GPR64[] = {
X86::R8, X86::R9, X86::R10, X86::R11,
X86::R12, X86::R13, X86::R14, X86::R15
};
- for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI;
- ++AI)
+ for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
Reserved.set(Reg);
// XMM8, XMM9, ...
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