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* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-5/+4
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Put the shiny new MCSubRegIterator to work.Chad Rosier2012-06-011-8/+6
| | | | llvm-svn: 157783
* s/CSR_Ghc/CSR_NoRegs/Jakob Stoklund Olesen2012-05-081-2/+2
| | | | | | | | | Share the CalleeSavedRegs defs between all calling conventions having no callee-saved registers. Patch by Yiannis Tsiouris! llvm-svn: 156382
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-1/+2
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* This patch marks the X86 floating point stack registers ST0-ST7 as reservedPreston Gurd2012-05-011-0/+10
| | | | | | | | | in order to avoid assertion failures in the register scavenger. The assertion failures were “Bad machine code: Using an undefined physical register” and “Bad machine code: MBB exits via unconditional fall-through but its successor differs from its CFG successor!”. llvm-svn: 155930
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. llvm-svn: 155395
* Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-1/+1
| | | | | | since they are equivalent. llvm-svn: 155186
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-3/+3
| | | | llvm-svn: 152001
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-1/+1
| | | | | | size of static data. llvm-svn: 151996
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-4/+0
| | | | llvm-svn: 148578
* Move X86 callee saved register lists to the X86CallConv .td file.Jakob Stoklund Olesen2012-01-171-37/+21
| | | | | | Add a trivial implementation of the getCallPreservedMask() hook. llvm-svn: 148347
* Emit a getMatchingSuperRegClass() implementation for every target.Jakob Stoklund Olesen2011-12-191-114/+6
| | | | | | | | | Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. llvm-svn: 146873
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-1/+1
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* For 64-bit the rest of the general regs are ok for the q constraint. MakeEric Christopher2011-12-011-1/+17
| | | | | | | | sure we can emit both the high and low versions of those registers. Fixes rdar://10392864 llvm-svn: 145579
* Prevent potential NOREX bug.Jakob Stoklund Olesen2011-10-081-0/+11
| | | | | | | | | | | | | | | A GR8_NOREX virtual register is created when extrating a sub_8bit_hi sub-register: %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1 TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2 If such a live range is ever split, its register class must not be inflated to GR8. The sub-register copy can only target GR8_NOREX. I dont have a test case for this theoretical bug. llvm-svn: 141500
* Override TRI::getSubClassWithSubReg for X86.Jakob Stoklund Olesen2011-10-051-0/+12
| | | | | | | | There are fewer registers with sub_8bit sub-registers in 32-bit mode than in 64-bit mode. In 32-bit mode, sub_8bit behaves the same as sub_8bit_hi. llvm-svn: 141206
* Store sub-class lists as a bit vector.Jakob Stoklund Olesen2011-09-301-1/+1
| | | | | | | | | | | | | | This uses less memory and it reduces the complexity of sub-class operations: - hasSubClassEq() and friends become O(1) instead of O(N). - getCommonSubClass() becomes O(N) instead of O(N^2). In the future, TableGen will infer register classes. This makes it cheap to add them. llvm-svn: 140898
* Fix PR10884.Bruno Cardoso Lopes2011-09-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This PR basically reports a problem where a crash in generated code happened due to %rbp being clobbered: pushq %rbp movq %rsp, %rbp .... vmovmskps %ymm12, %ebp .... movq %rbp, %rsp popq %rbp ret Since Eric's r123367 commit, the default stack alignment for x86 32-bit has changed to be 16-bytes. Since then, the MaxStackAlignmentHeuristicPass hasn't been really used, but with AVX it becomes useful again, since per ABI compliance we don't always align the stack to 256-bit, but only when there are 256-bit incoming arguments. ReserveFP was only used by this pass, but there's no RA target hook that uses getReserveFP() to check for the presence of FP (since nothing was triggering the pass to run, the uses of getReserveFP() were removed through time without being noticed). Change this pass to use setForceFramePointer, which is properly called by MachineFunction hasFP method. The testcase is very big and dependent on RA, not sure if it's worth adding to test/CodeGen/X86. llvm-svn: 139939
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-181-1/+0
| | | | | | better location welcome). llvm-svn: 135438
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-133/+8
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-1/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in ↵Eli Friedman2011-07-141-1/+2
| | | | | | 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate. llvm-svn: 135120
* Add an assert (which should never trigger) that triggers on a testcase I'm ↵Eli Friedman2011-07-131-1/+3
| | | | | | looking at. llvm-svn: 135018
* Constify getCompactUnwindRegNum.Bill Wendling2011-07-061-2/+2
| | | | llvm-svn: 134527
* Use the correct registers on X86_64.Bill Wendling2011-06-301-4/+4
| | | | llvm-svn: 134208
* Add target a target hook to get the register number used by the compact unwindBill Wendling2011-06-301-0/+15
| | | | | | | encoding for the registers it knows about. Return -1 if it can't handle that register. llvm-svn: 134202
* Always adjust the stack pointer immediately after the call.Jakob Stoklund Olesen2011-06-291-0/+7
| | | | | | | | | | | | | | | | | | | Some x86-32 calls pop values off the stack, and we need to readjust the stack pointer after the call. This happens when ADJCALLSTACKUP is eliminated. It could happen that spill code was inserted between the CALL and ADJCALLSTACKUP instructions, and we would compute wrong stack pointer offsets for those frame index references. Fix this by inserting the stack pointer adjustment immediately after the call instead of where the ADJCALLSTACKUP instruction was erased. I don't have a test case since we don't currently insert code in that position. We will soon, though. I am testing a regalloc patch that didn't work on Linux because of this. llvm-svn: 134113
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-11/+5
| | | | llvm-svn: 134030
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-281-2/+1
| | | | llvm-svn: 134027
* Clean up the handling of the x87 fp stack to make it more robust.Jakob Stoklund Olesen2011-06-281-12/+0
| | | | | | | | | | | | | | | | | | | | Drop the FpMov instructions, use plain COPY instead. Drop the FpSET/GET instruction for accessing fixed stack positions. Instead use normal COPY to/from ST registers around inline assembly, and provide a single new FpPOP_RETVAL instruction that can access the return value(s) from a call. This is still necessary since you cannot tell from the CALL instruction alone if it returns anything on the FP stack. Teach fast isel to use this. This provides a much more robust way of handling fixed stack registers - we can tolerate arbitrary FP stack instructions inserted around calls and inline assembly. Live range splitting could sometimes break x87 code by inserting spill code in unfortunate places. As a bonus we handle floating point inline assembly correctly now. llvm-svn: 134018
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-271-1/+4
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-241-3/+4
| | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
* Get rid of one getStackAlignment(). RegisterInfo shouldn't need to know ↵Evan Cheng2011-06-231-3/+4
| | | | | | about stack alignment. llvm-svn: 133679
* SI, DI, BP, and SP don't have 8-bit sub-registers in x86 mode.Jakob Stoklund Olesen2011-06-171-2/+9
| | | | llvm-svn: 133308
* Remove custom allocation order boilerplate that is no longer needed.Jakob Stoklund Olesen2011-06-091-0/+19
| | | | | | | | | | | | | | | | | | | | The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. llvm-svn: 132781
* Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen2011-06-021-2/+1
| | | | | | No functional change. llvm-svn: 132455
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-301-10/+21
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
* Add a GR32_NOREX_NOSP register class and fix a bug where ↵Cameron Zwarich2011-05-271-1/+8
| | | | | | | | | getMatchingSuperRegClass() was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032. llvm-svn: 132225
* Add a method to TargetRegisterInfo to get the register number that the Win64 EHCharles Davis2011-05-241-0/+21
| | | | | | | scheme uses internally. Implement it for x86 (the only architecture that LLVM supports for which this matters right now). llvm-svn: 131969
* Reserve the segment registers on x86 to fix verifier failures in any code thatCameron Zwarich2011-05-181-0/+9
| | | | | | uses them. llvm-svn: 131591
* Fix X86RegisterInfo::getMatchingSuperRegClass for sub_8bit_hi.Jakob Stoklund Olesen2011-05-041-13/+8
| | | | | | | It is OK for B to be any GR8_ABCD_H superclass, the returned register class doesn't have to map surjectively onto B. llvm-svn: 130892
* Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on ↵Jakob Stoklund Olesen2011-04-261-0/+27
| | | | | | | | | | | | register class inflation. The hook will be used by the register allocator when recomputing register classes after removing constraints. Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure that the spill size doesn't change. llvm-svn: 130228
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Re-commit 127368 and 127371. They are exonerated.Evan Cheng2011-03-101-1/+1
| | | | llvm-svn: 127380
* Revert 127368 and 127371 for now.Evan Cheng2011-03-091-1/+1
| | | | llvm-svn: 127376
* Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng2011-03-091-1/+1
| | | | | | | | | | | | | flexible. If it returns a register class that's different from the input, then that's the register class used for cross-register class copies. If it returns a register class that's the same as the input, then no cross- register class copies are needed (normal copies would do). If it returns null, then it's not at all possible to copy registers of the specified register class. llvm-svn: 127368
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-071-0/+20
| | | | llvm-svn: 127175
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