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* improve encoding information for branches. We now know they haveChris Lattner2010-02-111-15/+14
| | | | | | | 8 or 32-bit immediates, which allows the new encoder to handle them. llvm-svn: 95927
* unbreak the build.Chris Lattner2010-02-111-1/+1
| | | | llvm-svn: 95915
* refactor the conditional jump instructions in the .td file toChris Lattner2010-02-111-61/+36
| | | | | | | use a multipattern that generates both the 1-byte and 4-byte versions from the same defm llvm-svn: 95901
* Fix "the the" and similar typos.Dan Gohman2010-02-101-1/+1
| | | | llvm-svn: 95781
* TableGen fragment refactoring.David Greene2010-02-091-0/+6
| | | | | | | | | Move some utility TableGen defs, classes, etc. into a common file so they may be used my multiple pattern files. We will use this for the AVX specification to help with the transition from the current SSE specification. llvm-svn: 95727
* fix incorrect encoding of SBB8mi that Kevin noticed.Chris Lattner2010-02-051-2/+2
| | | | llvm-svn: 95448
* teach X86MCInstLower to lower the MOV32r0 and MOV8r0 Chris Lattner2010-02-051-4/+4
| | | | | | pseudo instructions. llvm-svn: 95433
* factor code better in X86MCInstLower::Lower, teach it toChris Lattner2010-02-051-7/+8
| | | | | | lower the SETB* instructions. llvm-svn: 95431
* Added support for X86 instruction prefixes so llvm-mc can assemble them. TheKevin Enderby2010-02-031-4/+40
| | | | | | | | | | Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. llvm-svn: 95252
* Change TAILJMP's to be varargs and transfer implicit uses over from ↵Evan Cheng2010-01-311-3/+4
| | | | | | TCRETURN's. Otherwise the missing uses can make post-regalloc scheduling do bad things. This fixes 403.gcc. llvm-svn: 94950
* MC/X86 AsmParser: Handle absolute memory operands correctly. We were doingDaniel Dunbar2010-01-301-1/+6
| | | | | | | | | | | | something totally broken and parsing them as immediates, but the .td file also had the wrong match class so things sortof worked. Except, that is, that we would parse movl $0, %eax as movl 0, %eax Feel free to guess how well that worked. llvm-svn: 94869
* X86.td: Refactor to bring operands that use print_pcrel_imm together.Daniel Dunbar2010-01-301-18/+14
| | | | llvm-svn: 94861
* AsmMatcher/X86: Separate out sublass for memory operands that have no segmentDaniel Dunbar2010-01-301-1/+5
| | | | | | register, and use to cleanup a FIXME in X86AsmParser.cpp. llvm-svn: 94859
* Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add ↵Evan Cheng2010-01-121-19/+8
| | | | | | patterns first. llvm-svn: 93245
* Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS.Dan Gohman2010-01-121-6/+9
| | | | llvm-svn: 93229
* Extend r93152 to work on OR r, r. If the source set bits are known not to ↵Evan Cheng2010-01-111-7/+29
| | | | | | overlap, then select as an ADD instead. llvm-svn: 93191
* Revert 93158. It's breaking quite a few x86_64 tests.Evan Cheng2010-01-111-9/+6
| | | | llvm-svn: 93185
* Do not turn 8-bit OR to ADD since ADD8ri is not 3-addressfiable.Evan Cheng2010-01-111-4/+1
| | | | llvm-svn: 93182
* Re-instate MOV64r0 and MOV16r0, with adjustments to work with theDan Gohman2010-01-111-6/+9
| | | | | | | | new AsmPrinter. This is perhaps less elegant than describing them in terms of MOV32r0 and subreg operations, but it allows the current register to rematerialize them. llvm-svn: 93158
* Pattern top-level operators don't need to be restricted to aDan Gohman2010-01-111-1/+1
| | | | | | single user. The _su forms are intended for non-top-level nodes. llvm-svn: 93155
* Select an OR with immediate as an ADD if the input bits are known zero. This ↵Evan Cheng2010-01-111-5/+34
| | | | | | allow the instruction to be 3address-fied if needed. llvm-svn: 93152
* Fix what looks to me obvious instruction definition bugs.Evan Cheng2010-01-081-1/+2
| | | | | | | 1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses. 2. LCMPXCHG8B is loading 64 bit memory, not 32 bit. llvm-svn: 92985
* Remove the SDNPAssociative properties for the flags-producingDan Gohman2010-01-051-6/+6
| | | | | | | operators. Eli pointed out that it's not obvious what that would mean. llvm-svn: 92555
* Add SDNPCommutative and SDNPAssociative to several X86 target nodes.Dan Gohman2010-01-041-6/+12
| | | | | | This lets isel fold loads into them in more cases. llvm-svn: 92506
* PR5886: Make sure IMUL32m is marked as setting EFLAGS, so scheduling doesn'tEli Friedman2009-12-261-1/+1
| | | | | | do illegal stuff around it. No testcase because the issue is very fragile. llvm-svn: 92167
* really remove the instruction, don't just comment it outChris Lattner2009-12-231-7/+4
| | | | llvm-svn: 91976
* completely eliminate the MOV16r0 'instruction'. The onlyChris Lattner2009-12-231-2/+2
| | | | | | | interesting part of this is the divrem changes, which are already tested by CodeGen/X86/divrem.ll. llvm-svn: 91975
* stop pattern matching 16-bit zero's of a register to MOV16r0,Chris Lattner2009-12-231-4/+10
| | | | | | | | | instead use the appropriate subreggy thing. This generates identical code on some large apps (thanks to Evan's cross class coalescing stuff he did back in july). This means that MOV16r0 can go away completely in the future soon. llvm-svn: 91972
* Remove target attribute break-sse-dep. Instead, do not fold load into sse ↵Evan Cheng2009-12-221-2/+1
| | | | | | partial update instructions unless optimizing for size. llvm-svn: 91910
* On recent Intel u-arch's, folding loads into some unary SSE instructions canEvan Cheng2009-12-181-0/+2
| | | | | | | | | | | | | | | | | | | be non-optimal. To be precise, we should avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g. movss (%rdi), %xmm0 cvtss2sd %xmm0, %xmm0 instead of cvtss2sd (%rdi), %xmm0 An alternative method to break dependency is to clear the register first. e.g. xorps %xmm0, %xmm0 cvtss2sd (%rdi), %xmm0 llvm-svn: 91672
* Instruction fixes, added instructions, and AsmString changes in theSean Callanan2009-12-181-144/+586
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier llvm-svn: 91638
* Re-enable 91381 with fixes.Evan Cheng2009-12-161-6/+9
| | | | llvm-svn: 91489
* Use sbb x, x to materialize carry bit in a GPR. The result is all one's or ↵Evan Cheng2009-12-151-0/+22
| | | | | | all zero's. llvm-svn: 91381
* Fix an obvious bug. No test case since LEA16r is not being used.Evan Cheng2009-12-121-1/+1
| | | | llvm-svn: 91219
* Minor whitespace fixes.Dan Gohman2009-11-301-1/+0
| | | | llvm-svn: 90166
* Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.Dan Gohman2009-11-231-10/+0
| | | | | | | | Note that "hasDotLocAndDotFile"-style debug info was already broken; people wanting this functionality should implement it in the AsmPrinter/DwarfWriter code. llvm-svn: 89711
* Use a tab in INT3's asm string, for consistency.Dan Gohman2009-11-111-1/+1
| | | | llvm-svn: 86850
* Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this ↵Anton Korobeynikov2009-11-021-12/+16
| | | | | | | won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. PS: It seems that blackfin usage of copy_to_regclass is completely bogus! llvm-svn: 85766
* Initial x86 support for BlockAddresses.Dan Gohman2009-10-301-0/+5
| | | | llvm-svn: 85557
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-5/+5
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too.Dan Gohman2009-10-201-0/+2
| | | | llvm-svn: 84652
* remove strings from instructions who are never asmprinted.Chris Lattner2009-10-191-11/+6
| | | | | | | | | All of these "subreg32" modifier instructions are handled explicitly by the MCInst lowering phase. If they got to the asmprinter, they would explode. They should eventually be replace with correct use of subregs. llvm-svn: 84526
* remove the asmstring, it is now dead. Improve comment.Chris Lattner2009-09-201-3/+4
| | | | llvm-svn: 82390
* kill off printPICLabel now, it's specialness is handled byChris Lattner2009-09-201-5/+1
| | | | | | | the MachineInstr ->MCInst lowering process, not in the asmprinter. llvm-svn: 82388
* Add an intel syntax MCInstPrinter implementation. You can nowChris Lattner2009-09-201-2/+2
| | | | | | transcode from AT&T to intel syntax with "llvm-mc foo.s -output-asm-variant=1" llvm-svn: 82385
* Add support for using the FLAGS result of or, xor, and and instructionsDan Gohman2009-09-181-0/+228
| | | | | | | on x86, to avoid explicit test instructions. A few existing tests changed due to arbitrary register allocation differences. llvm-svn: 82263
* Added RCL and RCR (rotate left and right with aSean Callanan2009-09-181-0/+91
| | | | | | | carry bit) instructions to the Intel instruction tables. llvm-svn: 82260
* Added the LODS (load byte into register, usuallySean Callanan2009-09-161-0/+6
| | | | | | | as part string parsing) instructions to the Intel instruction tables. llvm-svn: 82089
* Added the LAR (load segment access rights)Sean Callanan2009-09-161-0/+13
| | | | | | instructions to the Intel instruction tables. llvm-svn: 82084
* Added the LOOP family of instructions to the IntelSean Callanan2009-09-161-0/+6
| | | | | | instruction tables. llvm-svn: 82083
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