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* Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the Kevin Enderby2010-04-281-4/+6
| | | | | | Operand size override prefix to be part of their records. llvm-svn: 102556
* Enable i16 to i32 promotion by default.Evan Cheng2010-04-281-6/+7
| | | | llvm-svn: 102493
* Rather than having a ton of patterns for double shift instructions, e.g. ↵Evan Cheng2010-04-281-128/+0
| | | | | | SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32). llvm-svn: 102485
* Fix obvious typos.Evan Cheng2010-04-271-2/+2
| | | | llvm-svn: 102467
* isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.Evan Cheng2010-04-211-1/+9
| | | | llvm-svn: 101979
* More work to allow dag combiner to promote 16-bit ops to 32-bit.Evan Cheng2010-04-171-0/+2
| | | | llvm-svn: 101621
* Fix ADD32rr_alt instruction encoding bug. Patch by Marius Wachtler.Evan Cheng2010-04-051-1/+1
| | | | llvm-svn: 100480
* Separate out the AES-NI instructions from the SSE4.2 instructions. AddEric Christopher2010-04-021-0/+1
| | | | | | | | | a new subtarget option for AES and check for the support. Add "westmere" line of processors and add AES-NI support to the core i7. Add a couple of TODOs for information I couldn't verify. llvm-svn: 100231
* revert r99743, this is saying that the repmovs instructinos have anChris Lattner2010-03-281-2/+4
| | | | | | *input* of other type, which is the VT. llvm-svn: 99749
* claiming to return other is pointless.Chris Lattner2010-03-281-4/+2
| | | | llvm-svn: 99743
* fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptestChris Lattner2010-03-281-14/+10
| | | | | | nodes all have an EFLAGS result when made by isel lowering. llvm-svn: 99736
* eliminate the last of the parallel's!Chris Lattner2010-03-271-7/+2
| | | | llvm-svn: 99700
* eliminate almost all the rest of the x86-32 parallels.Chris Lattner2010-03-271-157/+116
| | | | llvm-svn: 99686
* Teach TableGen to understand X.Y notation in the TSFlagsFields strings.Jakob Stoklund Olesen2010-03-251-1/+1
| | | | | | | Remove much horribleness from X86InstrFormats as a result. Similar simplifications are probably possible for other targets. llvm-svn: 99539
* eliminate a bunch more parallels now that schedulingChris Lattner2010-03-251-205/+150
| | | | | | | handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
* Disable folding loads into tail call in 32-bit PIC mode. It can introduce ↵Evan Cheng2010-03-251-1/+5
| | | | | | | | | | | | | | | | | illegal code like this: addl $12, %esp popl %esi popl %edi popl %ebx popl %ebp jmpl *__Block_deallocator-L1$pb(%esi) # TAILCALL The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class. The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit. llvm-svn: 99455
* Switch INC8r to defining its pattern in terms of X86inc_flagChris Lattner2010-03-241-4/+4
| | | | | | | and defining the add pattern with Pat<>, eliminating a use of parallel. llvm-svn: 99375
* switch SDTBinaryArithWithFlags to be a multiple-result node as well.Chris Lattner2010-03-241-4/+4
| | | | llvm-svn: 99370
* Switch SDTUnaryArithWithFlags to being modeled as a two-resultChris Lattner2010-03-241-2/+4
| | | | | | | | | | | | | | ISD node. The only change in the generated isel code are comments like: < // Src: (X86dec_flag:i16 GR16:i16:$src) --- > // Src: (X86dec_flag:i16:i32 GR16:i16:$src) because now it knows that X86dec_flag returns both an i16 (for the result) and an i32 (for EFLAGS) in this case. Wewt. llvm-svn: 99369
* remove useless or_is_add parallel's.Chris Lattner2010-03-241-12/+6
| | | | llvm-svn: 99359
* reduce nesting.Chris Lattner2010-03-241-9/+8
| | | | llvm-svn: 99358
* remove the patterns that I commented out in r98930, Dan verified Chris Lattner2010-03-191-211/+0
| | | | | | that they are dead. llvm-svn: 99000
* add a new SDNPVariadic SDNP node flag, and use it inChris Lattner2010-03-191-4/+5
| | | | | | | | dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
* comment out a bunch of parallel store patterns that apparentlyChris Lattner2010-03-191-10/+22
| | | | | | | can't match or just have no testcases. Will remove after confirmation from dan that they really are dead. llvm-svn: 98930
* Now that tblgen can handle matching implicit defs of instructionsChris Lattner2010-03-191-74/+59
| | | | | | | | | | | | | | | | | | | | | | | | | to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. llvm-svn: 98903
* outs come before ins.Chris Lattner2010-03-181-3/+3
| | | | llvm-svn: 98864
* fix the encoding of TAILJMPd. This fixes Benchmarks/Olden/bisortChris Lattner2010-03-161-2/+2
| | | | | | with the integrated assembler! llvm-svn: 98615
* fix PR6605, X86ISD::CMP always returns i32 (EFLAGS), notChris Lattner2010-03-141-1/+1
| | | | | | the operand type. llvm-svn: 98507
* add support for pentium class CPUs which do not have cmov,Chris Lattner2010-03-141-13/+46
| | | | | | PR4841. Patch by Craig Smith! llvm-svn: 98496
* Do not force indirect tailcall through fixed registers: eax, r11. Add ↵Evan Cheng2010-03-141-24/+59
| | | | | | support to allow loads to be folded to tail call instructions. llvm-svn: 98465
* MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen ↵Daniel Dunbar2010-03-091-9/+11
| | | | | | only" so they don't get selected by the asm matcher. llvm-svn: 98098
* MC/X86: Rename alternate spellings of CMP{8,16,32} and mark as "code gen ↵Daniel Dunbar2010-03-091-6/+12
| | | | | | only" so they don't get selected by the asm matcher. llvm-svn: 98097
* Fix the vmxon entry in the X86InstrInfo.td so it has the correct prefix bytesKevin Enderby2010-03-081-1/+1
| | | | | | for the encoding and is not the same as vmptrld. llvm-svn: 97992
* X86: Fix encoding for TEST{8,16,32}rr.Daniel Dunbar2010-03-081-3/+3
| | | | llvm-svn: 97982
* Correct immediate sizes.Chris Lattner2010-03-081-1/+1
| | | | llvm-svn: 97957
* Describe what's going on with mingw alloca and why do we need separate ↵Anton Korobeynikov2010-03-061-1/+9
| | | | | | instruction. llvm-svn: 97888
* Lower dynamic stack allocation on mingw32 to separate instruction.Anton Korobeynikov2010-03-061-3/+11
| | | | | | | We cannot use a normal call here since it has extra unmodelled side effects (it changes stack pointer). This should fix PR5292. llvm-svn: 97884
* Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH.Jakob Stoklund Olesen2010-03-041-8/+11
| | | | | | | | | These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG reads AX in order to avoid reading AH with a REX instruction. Fix PR6489. llvm-svn: 97742
* remove nvload and two patterns that use it which are Chris Lattner2010-03-031-23/+0
| | | | | | better done by dag combine. llvm-svn: 97633
* factor the 'in the default address space' check out to a singleChris Lattner2010-03-031-51/+30
| | | | | | | 'dsload' pattern. tblgen doesn't check patterns to see if they're textually identical. This allows better factoring. llvm-svn: 97630
* factor the 'sign extended from 8 bit' patterns better so Chris Lattner2010-03-031-9/+4
| | | | | | | | that they are not destination type specific. This allows tblgen to factor them and the type check is redundant with what the isel does anyway. llvm-svn: 97629
* The mayHaveSideEffects flag is no longer used.Dan Gohman2010-02-271-2/+2
| | | | llvm-svn: 97348
* DIV8r must define %AX since X86DAGToDAGISel::Select() sometimes uses itJakob Stoklund Olesen2010-02-241-1/+1
| | | | | | instead of %AL/%AH. llvm-svn: 97006
* remove a bunch of dead named arguments in input patterns,Chris Lattner2010-02-231-26/+26
| | | | | | though some look dubious afaict, these are all ok. llvm-svn: 96899
* Added the rdtscp instruction to the x86 instructionSean Callanan2010-02-131-0/+3
| | | | | | tables. llvm-svn: 96073
* Fixed encodings for invlpg, invept, and invvpid.Sean Callanan2010-02-131-3/+3
| | | | llvm-svn: 96065
* remove special cases for vmlaunch, vmresume, vmxoff, and swapgsChris Lattner2010-02-131-3/+3
| | | | | | fix swapgs to be spelled right. llvm-svn: 96058
* enhance the immediate field encoding to know whether the immediateChris Lattner2010-02-121-9/+10
| | | | | | is pc relative or not, mark call and branches as pcrel. llvm-svn: 96026
* Add support for a union type in LLVM IR. Patch by Talin!Chris Lattner2010-02-121-1/+1
| | | | llvm-svn: 96011
* X86: Fix definition for RCL/RCR.*m? operations -- they were getting representedDaniel Dunbar2010-02-121-39/+41
| | | | | | with "tied memory operands", which is wrong. llvm-svn: 95950
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