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* move rep aliases to td fileChris Lattner2010-10-301-0/+4
| | | | llvm-svn: 117822
* move sal aliases to .td file.Chris Lattner2010-10-301-0/+5
| | | | llvm-svn: 117821
* move a bunch more aliases from .cpp -> .td file.Chris Lattner2010-10-301-2/+18
| | | | llvm-svn: 117819
* move cmov aliases to .td file.Chris Lattner2010-10-301-20/+25
| | | | llvm-svn: 117818
* move setcc and jcc aliases from .cpp to .tdChris Lattner2010-10-301-0/+28
| | | | llvm-svn: 117817
* implement (and document!) the first kind of MC assembler alias, which Chris Lattner2010-10-301-0/+23
| | | | | | | just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. llvm-svn: 117815
* X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424.Michael J. Spencer2010-10-211-3/+3
| | | | llvm-svn: 116984
* Fix Whitespace.Michael J. Spencer2010-10-201-38/+38
| | | | llvm-svn: 116972
* Added a handful of x86-32 instructions that were missing so that llvm-mc wouldKevin Enderby2010-10-181-1/+39
| | | | | | | | | | be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
* Fix PR8365 by adding a more specialized Pat that checks if an 'and' withRafael Espindola2010-10-131-0/+5
| | | | | | 8 bit constants can be used. llvm-svn: 116403
* Initial va_arg support for x86-64. Patch by David Meyer!Dan Gohman2010-10-121-1/+10
| | | | llvm-svn: 116319
* Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.Jakob Stoklund Olesen2010-10-121-28/+0
| | | | | | | | | | | The reg-reg copies were no longer being generated since copyPhysReg copies physical registers only. The loads and stores are not necessary - The TC constraint is imposed by the TAILJMP and TCRETURN instructions, there should be no need for constrained loads and stores. llvm-svn: 116314
* reapply the patch reverted in r116033:Chris Lattner2010-10-081-14/+0
| | | | | | | | "Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'" With a critical fix: the add pseudos clobber EFLAGS. llvm-svn: 116039
* Revert "Reimplement (part of) the or -> add optimization. Matching 'or' intoDaniel Dunbar2010-10-081-0/+14
| | | | | | 'add'", which seems to have broken just about everything. llvm-svn: 116033
* Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'Chris Lattner2010-10-071-14/+0
| | | | | | | | | | | | | | | | | | | is general goodness because it allows ORs to be converted to LEA to avoid inserting copies. However, this is bad because it makes the generated .s file less obvious and gives valgrind heartburn (tons of false positives in bitfield code). While the general fix should be in valgrind, we can at least try to avoid emitting ADD instructions that *don't* get promoted to LEA. This is more work because it requires introducing pseudo instructions to represents "add that knows the bits are disjoint", but hey, people really love valgrind. This fixes this testcase: https://bugs.kde.org/show_bug.cgi?id=242137#c20 the add r/i cases are coming next. llvm-svn: 116007
* fix a bug I introduced in r115669, which ended up with MOV64mr_TCChris Lattner2010-10-051-1/+2
| | | | | | not getting marked as mayStore. This fixes llvm-gcc bootstrap. llvm-svn: 115693
* Replace a gross hack (the MOV64ri_alt instruction) with a slightly less Chris Lattner2010-10-051-9/+0
| | | | | | gross hack (having the asmmatcher handle the alias). llvm-svn: 115685
* distribute the rest of the contents of X86Instr64bit.td out toChris Lattner2010-10-051-111/+100
| | | | | | the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
* split the 32-bit integer arithmetic instructions out to their own file.Chris Lattner2010-10-051-1226/+4
| | | | llvm-svn: 115627
* move 32-bit shift and rotates out to their own file.Chris Lattner2010-10-051-555/+1
| | | | llvm-svn: 115607
* move sign and zero extensions out to their own file.Chris Lattner2010-10-051-88/+7
| | | | llvm-svn: 115605
* move some instructions from Instr64Bit -> InstrInfo.Chris Lattner2010-10-051-12/+69
| | | | | | bswap32 doesn't read eflags. llvm-svn: 115604
* move CMOV_FR32 and friends to InstrCompiler, since they are Chris Lattner2010-10-051-11/+5
| | | | | | | | pseudo instructions. Move POPCNT to InstrSSE since they are SSE4 instructions. llvm-svn: 115603
* move various pattern matching support goop out of X86Instr64Bit, to liveChris Lattner2010-10-051-0/+58
| | | | | | with the 32-bit stuff. llvm-svn: 115602
* split conditional moves and setcc's out to their own file.Chris Lattner2010-10-051-635/+1
| | | | llvm-svn: 115601
* move string pseudo instructions to InstrCompiler consolidate 64-bit and ↵Chris Lattner2010-10-051-18/+5
| | | | | | 32-bit together. llvm-svn: 115600
* move the atomic pseudo instructions out to X86InstrCompiler.tdChris Lattner2010-10-051-237/+35
| | | | llvm-svn: 115599
* move more pseudo instructions out to X86InstrCompiler.tdChris Lattner2010-10-051-105/+0
| | | | llvm-svn: 115598
* move VMX instructions out to their own file.Chris Lattner2010-10-051-40/+2
| | | | llvm-svn: 115597
* continue moving stuff out to X86InstrSystem.td. MoveChris Lattner2010-10-051-733/+9
| | | | | | | | control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
* refactor .td files a bit, moving system instructions out to X86InstrSystem.tdChris Lattner2010-10-051-280/+9
| | | | llvm-svn: 115591
* Implement support for the bizarre 3DNow! encoding (which is unlike anythingChris Lattner2010-10-031-0/+2
| | | | | | | | | | | else in X86), and add support for pavgusb. This is apparently the only instruction (other than movsx) that is preventing ffmpeg from building with clang. If someone else is interested in banging out the rest of the 3DNow! instructions, it should be quite easy now. llvm-svn: 115466
* stub out a header to put 3dNow! instructions into.Chris Lattner2010-10-021-0/+2
| | | | llvm-svn: 115429
* Revert r114703 and r114702, removing the isConditionalMove flag from ↵Owen Anderson2010-09-231-2/+2
| | | | | | | | instructions. After further reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board! llvm-svn: 114710
* Add isConditionalMove bits to X86 and ARM instructions.Owen Anderson2010-09-231-2/+2
| | | | llvm-svn: 114703
* Fix an inconsistency in the x86 backend that led it to reject "calll foo" onChris Lattner2010-09-221-3/+5
| | | | | | | | | | | | x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly named "callq", so this only impacted x86-32. This fixes rdar://8456370 - llvm-mc rejects 'calll' This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call, I will file a bugzilla. llvm-svn: 114534
* reimplement elf TLS support in terms of addressing modes, eliminating ↵Chris Lattner2010-09-221-4/+0
| | | | | | SegmentBaseAddress. llvm-svn: 114529
* give VZEXT_LOAD a memory operand, it now works with segment registers.Chris Lattner2010-09-221-2/+2
| | | | llvm-svn: 114515
* reimplement support for GS and FS relative address space matchingChris Lattner2010-09-211-39/+6
| | | | | | | | | | | | | | | | | by having X86DAGToDAGISel::SelectAddr get passed in the parent node of the operand match (the load/store/atomic op) and having it get the address space from that, instead of having special FS/GS addr mode operations that require duplicating the entire instruction set to support. This makes FS and GS relative accesses *far* more predictable and work much better. It also simplifies the X86 backend a bit, more to come. There is still a pending issue with nodes like ISD::PREFETCH and X86ISD::FLD, which really should be MemSDNode's but aren't. llvm-svn: 114491
* even though I'm about to rip it out, simplify the address mode stuffChris Lattner2010-09-211-24/+11
| | | | llvm-svn: 114468
* fix rdar://8444631 - encoder crash on 'enter'Chris Lattner2010-09-171-2/+2
| | | | | | What a weird instruction. llvm-svn: 114190
* fix the encoding of sldt GR16 to have the 0x66 prefix, andChris Lattner2010-09-151-1/+3
| | | | | | | add sldt GR32, which isn't documented in the intel manual but which gas accepts. Part of rdar://8418316 llvm-svn: 113938
* fix bugs in push/pop segment support, rdar://8407242Chris Lattner2010-09-081-5/+35
| | | | llvm-svn: 113422
* implement proper support for sysret{,l,q}, rdar://8403907Chris Lattner2010-09-081-2/+2
| | | | llvm-svn: 113350
* implement the iret suite of instructions properly,Chris Lattner2010-09-081-2/+2
| | | | | | fixing rdar://8403974 llvm-svn: 113349
* fix the encoding of the "jump on *cx" family of instructions,Chris Lattner2010-09-081-4/+22
| | | | | | rdar://8061602 llvm-svn: 113343
* Remove a dead comment.Evan Cheng2010-09-071-1/+0
| | | | llvm-svn: 113259
* fix the operand constraints of the immediate form of in/out,Chris Lattner2010-09-061-6/+6
| | | | | | allowing unsigned 8-bit operands. This fixes rdar://8208481 llvm-svn: 113182
* Redefine LOOP* instructions from I to Ii8PCRel as they take an i8 argument.Roman Divacky2010-09-061-3/+3
| | | | llvm-svn: 113158
* Don't call Predicate_* from X86 target.Jakob Stoklund Olesen2010-09-031-3/+1
| | | | llvm-svn: 112921
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