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* Add a new bit that ImmLeaf's can opt into, which allows them to duck out ofChris Lattner2011-04-181-3/+6
| | | | | | | | the generated FastISel. X86 doesn't need to generate code to match ADD16ri8 since ADD16ri will do just fine. This is a small codesize win in the generated instruction selector. llvm-svn: 129692
* switch the rest of the x86 immediate patterns over to ImmLeaf, Chris Lattner2011-04-171-17/+9
| | | | | | | simplifying them and exposing more information to tblgen. It would be nice if other target authors adopted this as well, particularly arm since it has fastisel. llvm-svn: 129676
* now that predicates have a decent abstraction layer on them, introduce a new Chris Lattner2011-04-171-1/+6
| | | | | | | | | kind of predicate: one that is specific to imm nodes. The predicate function specified here just checks an int64_t directly instead of messing around with SDNode's. The virtue of this is that it means that fastisel and other things can reason about these predicates. llvm-svn: 129675
* Rework our internal representation of node predicates to expose moreChris Lattner2011-04-171-1/+1
| | | | | | | | structure and fix some fixmes. We now have a TreePredicateFn class that handles all of the decoding of these things. This is an internal cleanup that has no impact on the code generated by tblgen. llvm-svn: 129670
* As Dan pointed out, movzbl, movsbl, and friends are nicer than their aliasBill Wendling2011-04-141-13/+13
| | | | | | (movzx/movsx) because they give more information. Revert that part of the patch. llvm-svn: 129498
* Have the X86 back-end emit the alias instead of what's being aliased. In mostBill Wendling2011-04-141-10/+12
| | | | | | cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
* Add an option to not print the alias of an instruction. It defaults to "printBill Wendling2011-04-131-2/+4
| | | | | | the alias". llvm-svn: 129485
* Recognize loopz and loopnz as aliases for loope and loopne.Joerg Sonnenberger2011-02-221-0/+3
| | | | | | From Dimitry Andric. llvm-svn: 126168
* implement PR9264: disambiguating 'bt mem, imm' as a btl.Chris Lattner2011-02-191-0/+3
| | | | | | | This is reasonable to do since all bt-mem forms do the same thing. llvm-svn: 126047
* Recognize leavel and leaveq aliases for leave.Joerg Sonnenberger2011-02-171-0/+3
| | | | | | Validate encoding of leave in 64bit mode. llvm-svn: 125795
* Target/X86: Tweak win64's tailcall.NAKAMURA Takumi2011-01-261-1/+6
| | | | llvm-svn: 124272
* Fix whitespace.NAKAMURA Takumi2011-01-261-2/+1
| | | | llvm-svn: 124270
* Add another non-commutable instruction that gas accepts commuted forms for.Nick Lewycky2010-12-301-3/+4
| | | | | | Fixes PR8861. llvm-svn: 122641
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-13/+13
| | | | llvm-svn: 122513
* Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (whichChris Lattner2010-12-201-0/+10
| | | | | | | | | | | | | their carry depenedencies with MVT::Flag operands) and use clean and beautiful EFLAGS dependences instead. We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs (which is what requires the previous scheduler change) and change X86 ISelLowering to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes. With the previous series of changes, this causes no changes in the testsuite, woo. llvm-svn: 122213
* Formalize the notion that AVX and SSE are non-overlapping extensions from ↵Nate Begeman2010-12-101-14/+13
| | | | | | the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
* Rewrite the darwin tlv support to use a chain and return to copyingEric Christopher2010-12-091-2/+2
| | | | | | | | the output to the correct register. Fixes a hidden problem uncovered by the last patch where we'd try to DAG combine our MVT::Other node oddly. llvm-svn: 121358
* it turns out that when ".with.overflow" intrinsics were added to the X86Chris Lattner2010-12-051-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | backend that they were all implemented except umul. This one fell back to the default implementation that did a hi/lo multiply and compared the top. Fix this to check the overflow flag that the 'mul' instruction sets, so we can avoid an explicit test. Now we compile: void *func(long count) { return new int[count]; } into: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] seto %cl ## encoding: [0x0f,0x90,0xc1] testb %cl, %cl ## encoding: [0x84,0xc9] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL instead of: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL Other than the silly seto+test, this is using the o bit directly, so it's going in the right direction. llvm-svn: 120935
* Revert this change since it breaks a couple of the AVX tests.Nate Begeman2010-12-031-7/+12
| | | | | | I'm unclear if the tests are actually correct or not, but reverting for now. llvm-svn: 120847
* Remove SSE1-4 disable when AVX is enabled. While this may be useful for ↵Nate Begeman2010-12-031-12/+7
| | | | | | | | development, it completely breaks scalar fp in xmm regs when AVX is enabled. llvm-svn: 120843
* Implement the data16 prefix.Rafael Espindola2010-11-271-0/+3
| | | | llvm-svn: 120224
* Implement the rex64 prefix.Rafael Espindola2010-11-231-0/+3
| | | | llvm-svn: 120017
* implement PR8524, apparently mainline gas accepts movq as an alias for movdChris Lattner2010-11-211-0/+4
| | | | | | when transfering between i64 gprs and mmx regs. llvm-svn: 119931
* accept lret as an alias for lretl, fixing the reopened part of PR8592Chris Lattner2010-11-121-0/+3
| | | | llvm-svn: 118916
* implement aliases for div/idiv that have an explicit A register operand,Chris Lattner2010-11-061-0/+20
| | | | | | implementing rdar://8431864 llvm-svn: 118364
* add aliases for movs between seg registers and mem. There are multipleChris Lattner2010-11-061-0/+5
| | | | | | | | | | different forms of this instruction (movw/movl/movq) which we reported as being ambiguous. Since they all do the same thing, gas just picks the one with the shortest encoding. Follow its lead here. This implements rdar://8208615 llvm-svn: 118362
* move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.Chris Lattner2010-11-061-2/+18
| | | | llvm-svn: 118361
* work-in-progressChris Lattner2010-11-061-7/+6
| | | | llvm-svn: 118358
* go to great lengths to work around a GAS bug my previous patchChris Lattner2010-11-061-6/+6
| | | | | | | | | | | | | | | | exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. llvm-svn: 118356
* rework the rotate-by-1 instructions to be defined like theChris Lattner2010-11-061-0/+27
| | | | | | | | | | | | | shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. llvm-svn: 118355
* change the fp comparison instructions to not have %st0 explicitlyChris Lattner2010-11-061-8/+5
| | | | | | | listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
* move the plethora of fp stack aliases to the .td file.Chris Lattner2010-11-061-7/+48
| | | | llvm-svn: 118353
* add (and document) the ability for alias results to haveChris Lattner2010-11-061-0/+13
| | | | | | | | fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). llvm-svn: 118352
* generalize alias support to allow the result of an alias toChris Lattner2010-11-061-0/+4
| | | | | | | add fixed immediate values. Move the aad and aam aliases to use this, and document it. llvm-svn: 118350
* move fnstsw aliases to .td file, fix typoChris Lattner2010-11-061-1/+6
| | | | llvm-svn: 118349
* move in/out aliases to the .td files.Chris Lattner2010-11-061-0/+16
| | | | llvm-svn: 118348
* move sldt, imul, and movabsq aliases from c++ to .td file.Chris Lattner2010-11-061-0/+18
| | | | llvm-svn: 118347
* fix a bug where we had an implicit assumption that theChris Lattner2010-11-061-6/+14
| | | | | | | | result instruction operand numbering matched the result pattern. Fixing this allows us to move the xchg/test aliases to the .td file. llvm-svn: 118334
* move the lcall/ljmp aliases to the .td file.Chris Lattner2010-11-061-4/+20
| | | | llvm-svn: 118332
* move the "movsd -> movsl" alias to the .td files, Chris Lattner2010-11-061-30/+17
| | | | | | tidy up the movsx and movzx aliases. llvm-svn: 118331
* fix some bugs in the alias support, unblocking changing of "clr" aliasesChris Lattner2010-11-061-0/+6
| | | | | | from c++ hacks to proper .td InstAlias definitions. Change them! llvm-svn: 118330
* Reimplement BuildResultOperands to be in terms of the result instruction'sChris Lattner2010-11-061-26/+13
| | | | | | | | | | | | | | | | | | operand list instead of the operand list redundantly declared on the alias or instruction. With this change, we finally remove the ins/outs list on the alias. Before: def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), "movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; After: def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; This also makes the alias mechanism more general and powerful, which will be exploited in subsequent patches. llvm-svn: 118329
* rearrange a bit.Chris Lattner2010-11-011-50/+55
| | | | llvm-svn: 117967
* use our fancy new MnemonicAlias mechanism to remove a bunch of hacksChris Lattner2010-11-011-3/+16
| | | | | | from X86AsmParser.cpp llvm-svn: 117952
* "mov[zs]x (mem), GR16" are not ambiguous: the memChris Lattner2010-11-011-0/+6
| | | | | | must be 8 bits. Support this memory form. llvm-svn: 117902
* Implement enough of the missing instalias support to getChris Lattner2010-11-011-0/+33
| | | | | | | | | | | | | | | | | | aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. llvm-svn: 117901
* sketch out the planned instruction alias mechanism, add some comments aboutChris Lattner2010-10-311-0/+14
| | | | | | how the push/pop mnemonic aliases are wrong. llvm-svn: 117857
* Resolve a terrible hack in tblgen: instead of hardcodingChris Lattner2010-10-301-2/+2
| | | | | | | "In32BitMode" and "In64BitMode" into tblgen, allow any predicate that inherits from AssemblerPredicate. llvm-svn: 117831
* Implement (and document!) support for MnemonicAlias's to have Requires Chris Lattner2010-10-301-1/+13
| | | | | | | | | | | directives, allowing things like this: def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; Move the rest of the X86 MnemonicAliases over to the .td file. llvm-svn: 117830
* move fcompi alias to .td file and zap some useless code.Chris Lattner2010-10-301-0/+1
| | | | llvm-svn: 117823
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