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* Add predicate method check match memory operand size, if available.Devang Patel2012-01-121-14/+46
| | | | | | In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
* Instruction selection priority fixes to remove the XMM/XMMInt/orAVX ↵Craig Topper2012-01-101-8/+2
| | | | | | predicates. Another commit will remove orAVX functions from X86SubTarget. llvm-svn: 147841
* Don't disable MMX support when AVX is enabled. Fix predicates for MMX ↵Craig Topper2012-01-091-0/+1
| | | | | | instructions that were added along with SSE instructions to check for AVX in addition to SSE level. llvm-svn: 147762
* Allow CRC32 instructions to be selected when AVX is enabled.Craig Topper2012-01-011-0/+1
| | | | llvm-svn: 147411
* Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX ↵Craig Topper2012-01-011-0/+1
| | | | | | is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. llvm-svn: 147409
* XOP instructions and encoding tests.Jan Sjödin2011-12-121-0/+4
| | | | llvm-svn: 146407
* Remove hasSSE1orAVX(). It's the same as hasXMM().Evan Cheng2011-12-091-2/+0
| | | | llvm-svn: 146246
* Many of the SSE patterns should not be selected when AVX is available. This ↵Evan Cheng2011-12-081-0/+2
| | | | | | | | | | | | | | | | | | led to the following code in X86Subtarget.cpp if (HasAVX) X86SSELevel = NoMMXSSE; This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected. However, this breaks instructions which do not have AVX variants. The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX(). Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change. However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case, the prefetch instructions. rdar://10538297 llvm-svn: 146163
* Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.Jakob Stoklund Olesen2011-11-291-0/+1
| | | | | | | | | Like V_SET0, these instructions are expanded by ExpandPostRA to xorps / vxorps so they can participate in execution domain swizzling. This also makes the AVX variants redundant. llvm-svn: 145440
* X86: alias cqo to cqto.Benjamin Kramer2011-11-241-1/+2
| | | | llvm-svn: 145121
* Add intrinsics and feature flag for read/write FS/GS base instructions. Also ↵Craig Topper2011-10-301-0/+2
| | | | | | add AVX2 feature flag. llvm-svn: 143319
* Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix andKevin Enderby2011-10-271-0/+1
| | | | | | | not depend on In32BitMode. Use the sysexitq mnemonic for the version with the REX.W prefix and only allow it only In64BitMode. rdar://9738584 llvm-svn: 143112
* Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with ↵Craig Topper2011-10-211-10/+14
| | | | | | custom isel lowering code. llvm-svn: 142642
* Rename PEXTR to PEXT. Add intrinsics for BMI instructions.Craig Topper2011-10-191-24/+47
| | | | llvm-svn: 142480
* Remove NaClModeDavid Meyer2011-10-181-8/+2
| | | | llvm-svn: 142338
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-161-0/+17
| | | | llvm-svn: 142141
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-161-8/+14
| | | | llvm-svn: 142122
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper2011-10-161-11/+23
| | | | | | 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper2011-10-151-1/+21
| | | | | | because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-141-0/+1
| | | | llvm-svn: 141947
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-141-0/+32
| | | | | | processor which is gcc's name for Haswell. llvm-svn: 141939
* Ban rematerializable instructions with side effects.Jakob Stoklund Olesen2011-10-141-1/+1
| | | | | | | | | | TableGen infers unmodeled side effects on instructions without a pattern. Fix some instruction definitions where that was overlooked. Also raise an error if a rematerializable instruction has unmodeled side effects. That doen't make any sense. llvm-svn: 141929
* Revert r141854 because it was causing failures:Bill Wendling2011-10-131-32/+0
| | | | | | | | | | | | | | | http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101 --- Reverse-merging r141854 into '.': U test/MC/Disassembler/X86/x86-32.txt U test/MC/Disassembler/X86/simple-tests.txt D test/CodeGen/X86/bmi.ll U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86.td U lib/Target/X86/X86Subtarget.h llvm-svn: 141857
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-131-0/+32
| | | | | | processor which is gcc's name for Haswell. llvm-svn: 141854
* Add 'implicit EFLAGS' to patterns for popcnt and lzcntCraig Topper2011-10-131-6/+11
| | | | llvm-svn: 141853
* Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as ↵Craig Topper2011-10-111-0/+1
| | | | | | modifying EFLAGS. llvm-svn: 141656
* Add X86 LZCNT instruction. Including instruction selection support.Craig Topper2011-10-111-0/+27
| | | | llvm-svn: 141651
* X86: Add patterns for the movbe instruction (mov + bswap, only available on ↵Benjamin Kramer2011-10-101-6/+12
| | | | | | atom) llvm-svn: 141563
* Add Ivy Bridge 16-bit floating point conversion instructions for the X86 ↵Craig Topper2011-10-091-0/+1
| | | | | | disassembler. llvm-svn: 141505
* Revert part of r141274. Only need to change encoding for xchg %eax, %eax in ↵Craig Topper2011-10-071-7/+12
| | | | | | 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. llvm-svn: 141353
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper2011-10-061-3/+8
| | | | | | was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. llvm-svn: 141274
* Add support for MOVBE and RDRAND instructions for the assembler and ↵Craig Topper2011-10-031-0/+32
| | | | | | disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
* Fix some Intel syntax disassembly issues with instructions that implicitly ↵Craig Topper2011-10-021-13/+13
| | | | | | use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. llvm-svn: 140974
* Fix handling of Intel syntax disassembling of movs and stos to stop being ↵Craig Topper2011-09-091-12/+12
| | | | | | blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875. llvm-svn: 139353
* Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certainNick Lewycky2011-09-051-0/+8
| | | | | | | instructions are more aligned than the CPU requires, and adds some additional directives, to follow in future patches. Patch by David Meyer! llvm-svn: 139125
* Adds a SelectionDAG node X86SegAlloca which will be custom loweredRafael Espindola2011-08-301-0/+5
| | | | | | | | | | | | from DYNAMIC_STACKALLOC. Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which will match X86SegAlloca (based on word size) are also added. They will be custom emitted to inject the actual stack handling code. Patch by Sanjoy Das. llvm-svn: 138814
* Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.Eli Friedman2011-08-261-3/+8
| | | | llvm-svn: 138660
* X86: Add some operand types required to identify calls.Benjamin Kramer2011-08-221-0/+2
| | | | llvm-svn: 138285
* Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.Kevin Enderby2011-07-271-0/+16
| | | | | | | | | | | | llvm-mc gives an "invalid operand" error for instructions that take an unsigned immediate which have the high bit set such as: pblendw $0xc5, %xmm2, %xmm1 llvm-mc treats all x86 immediates as signed values and range checks them. A small number of x86 instructions use the imm8 field as a set of bits. This change only changes those instructions and where the high bit is not ignored. The others remain unchanged. llvm-svn: 136287
* Port operand types for ARM and X86 over from EDIS to the .td files.Benjamin Kramer2011-07-141-1/+11
| | | | llvm-svn: 135198
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-2/+4
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that aKevin Enderby2011-07-061-1/+1
| | | | | | push with a small constant produces a 2-byte push. llvm-svn: 134501
* Reapply 132424 with fixes. This fixes PR10068.Stuart Hastings2011-06-031-0/+3
| | | | | | rdar://problem/5993888 llvm-svn: 132606
* Revert 132424 to fix PR10068.Rafael Espindola2011-06-021-3/+0
| | | | llvm-svn: 132479
* Recommit 132404 with fixes. rdar://problem/5993888Stuart Hastings2011-06-011-0/+3
| | | | llvm-svn: 132424
* Revert 132404 to appease a buildbot. rdar://problem/5993888Stuart Hastings2011-06-011-3/+0
| | | | llvm-svn: 132419
* Add support for x86 CMPEQSS and friends. These instructions do aStuart Hastings2011-06-011-0/+3
| | | | | | | | floating-point comparison, generate a mask of 0s or 1s, and generally DTRT with NaNs. Only profitable when the user wants a materialized 0 or 1 at runtime. rdar://problem/5993888 llvm-svn: 132404
* add a missing alias to make us more bug compatible with gcc, PR9378Chris Lattner2011-05-221-0/+1
| | | | llvm-svn: 131874
* Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.Stuart Hastings2011-05-201-4/+4
| | | | | | rdar://problem/8614450 llvm-svn: 131746
* This should always be signed chars, so use int8_t. This fixes a miscompile whenNick Lewycky2011-04-201-3/+3
| | | | | | | | llvm is built with unsigned chars where an immediate such as 0xff would be zero extended to 64-bits, turning "cmp $0xff,%eax" into "cmp $0xffffffffffffffff,%eax". llvm-svn: 129845
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