summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/X86InstrInfo.td
Commit message (Collapse)AuthorAgeFilesLines
...
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-281-0/+19
| | | | llvm-svn: 178314
* Skip moving call address loading into callseq when targets prefer register ↵Michael Liao2013-03-281-0/+1
| | | | | | | | | | | | | | | | | | indirect call. To enable a load of a call address to be folded with that call, this load is moved from outside of callseq into callseq. Such a moving adds a non-glued node (that load) into a glued sequence. This non-glue load is only removed when DAG selection folds them into a memory form call instruction. When such instruction selection is disabled, it breaks DAG schedule. To prevent that, such moving is disabled when target favors register indirect call. Previous workaround disabling CALL32m/CALL64m insn selection is removed. llvm-svn: 178308
* Add XTEST codegen supportMichael Liao2013-03-261-0/+1
| | | | llvm-svn: 178083
* Add HLE target featureMichael Liao2013-03-261-0/+1
| | | | llvm-svn: 178082
* Annotate the rest of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen2013-03-261-27/+43
| | | | llvm-svn: 178048
* Add PREFETCHW codegen supportMichael Liao2013-03-261-0/+2
| | | | | | - Add 'PRFCHW' feature defined in AVX2 ISA extension llvm-svn: 178040
* Add a WriteMicrocoded for ancient microcoded instructions.Jakob Stoklund Olesen2013-03-211-0/+4
| | | | llvm-svn: 177611
* Annotate a lot of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen2013-03-191-26/+60
| | | | llvm-svn: 177417
* [ms-inline asm] Add support for the pushad/popad mnemonics.Chad Rosier2013-02-251-4/+2
| | | | | | rdar://13254235 llvm-svn: 176036
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-141-0/+1
| | | | | | -feature flag, instructions definitions, test cases llvm-svn: 175196
* Two changes relevant to LEA and x32:David Sehr2013-02-011-0/+13
| | | | | | | | | 1) allows the use of RIP-relative addressing in 32-bit LEA instructions under x86-64 (ILP32 and LP64) 2) separates the size of address registers in 64-bit LEA instructions from control by ILP32/LP64. llvm-svn: 174208
* Remove # from the beginning and end of def names.Craig Topper2013-01-071-26/+26
| | | | llvm-svn: 171696
* Adds missing aliases for fcom and fcomp instructions without arguments.Kevin Enderby2013-01-021-0/+2
| | | | | | Patch by Michael M Kuperstein! llvm-svn: 171414
* Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC ↵Craig Topper2012-12-271-19/+43
| | | | | | instructions. Shouldn't change any functionality since they don't have patterns to select them. llvm-svn: 171128
* Fix operands and encoding form for ARPL instruction. Register form had and ↵Craig Topper2012-12-261-2/+2
| | | | | | reversed. Memory form writes memory, but was marked as MRMSrcMem. llvm-svn: 171123
* Mark all the _REV instructions as not having side effects. They aren't ↵Craig Topper2012-12-261-1/+1
| | | | | | really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. llvm-svn: 171118
* Remove EFLAGS from the BLSI/BLSMSK/BLSR patterns. The nodes created by DAG ↵Craig Topper2012-12-171-11/+11
| | | | | | combine don't contain an EFLAGS def. llvm-svn: 170308
* X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.Jim Grosbach2012-11-141-2/+2
| | | | | | | | | | When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 llvm-svn: 167937
* Add support of RTM from TSX extensionMichael Liao2012-11-081-0/+3
| | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
* Add __builtin_setjmp/_longjmp supprt in X86 backendMichael Liao2012-10-151-0/+8
| | | | | | | | | | | - Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also used as a light-weight replacement of setjmp/longjmp which are used to implementation continuation, user-level threading, and etc. The support added in this patch ONLY addresses this usage and is NOT intended to support SjLj exception handling as zero-cost DWARF exception handling is used by default in X86. llvm-svn: 165989
* Separate AVXCC and SSECC printing for cmpps/pd/ss/sd and add masking before ↵Craig Topper2012-10-091-1/+1
| | | | | | the switch statement. This keeps the unreachable default case from being hit if the instruction was created with an intrinsic with too large of an immediate. llvm-svn: 165483
* Remove hasNoAVX method. Can just invert hasAVX instead.Craig Topper2012-09-261-6/+6
| | | | llvm-svn: 164664
* Revise td of X86 atomic instructionsMichael Liao2012-09-211-19/+38
| | | | | | | - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
* Revert r163761 "Don't fold indexed loads into TCRETURNmi64."Jakob Stoklund Olesen2012-09-131-4/+0
| | | | | | The patch caused "Wrong topological sorting" assertions. llvm-svn: 163810
* Don't fold indexed loads into TCRETURNmi64.Jakob Stoklund Olesen2012-09-131-0/+4
| | | | | | | | | | | | | We don't have enough GR64_TC registers when calling a varargs function with 6 arguments. Since %al holds the number of vector registers used, only %r11 is available as a scratch register. This means that addressing modes using both base and index registers can't be folded into TCRETURNmi64. <rdar://problem/12282281> llvm-svn: 163761
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-101-2/+2
| | | | llvm-svn: 163561
* Introduce 'UseSSEx' to force SSE legacy encodingMichael Liao2012-08-301-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is enabled. As the penalty of inter-mixing SSE and AVX instructions, we need prevent SSE legacy insn from being generated except explicitly specified through some intrinsics. For patterns supported by both SSE and AVX, so far, we force AVX insn will be tried first relying on AddedComplexity or position in td file. It's error-prone and introduces bugs accidentally. 'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited by AVX, we need this predicate to force VEX encoding or SSE legacy encoding only. For insns not inherited by AVX, we still use the previous predicates, i.e. 'HasSSEx'. So far, these insns fall into the following categories: * SSE insns with MMX operands * SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH, CRC, and etc.) * SSE4A insns. * MMX insns. * x87 insns added by SSE. 2 test cases are modified: - test/CodeGen/X86/fast-isel-x86-64.ll AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be selected by fast-isel due to complicated pattern and fast-isel fallback to materialize it from constant pool. - test/CodeGen/X86/widen_load-1.ll AVX code generation is different from SSE one after fixing SSE/AVX inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of 'vmovaps'. llvm-svn: 162919
* Add HasAVX1Only predicate and use it for patterns that have an AVX1 ↵Craig Topper2012-08-271-0/+1
| | | | | | instruction and an AVX2 instruction rather than relying on AddedComplexity. llvm-svn: 162654
* X86MemBarrier has unmodeled side effects.Jakob Stoklund Olesen2012-08-241-1/+1
| | | | llvm-svn: 162514
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-181-4/+26
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
* Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and ↵Benjamin Kramer2012-07-121-1/+2
| | | | | | | | MachineLICM don't touch it. I already had the necessary things in place for IR-level passes but missed the machine passes. llvm-svn: 160137
* Add intrinsics for Ivy Bridge's rdrand instruction.Benjamin Kramer2012-07-121-3/+10
| | | | | | | | | The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. llvm-svn: 160117
* X86: add more GATHER intrinsics in LLVMManman Ren2012-06-291-4/+2
| | | | | | | | | | | | | | | Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 llvm-svn: 159402
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-0/+8
| | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
* Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.Craig Topper2012-06-031-1/+1
| | | | llvm-svn: 157903
* Implement the local-dynamic TLS model for x86 (PR3985)Hans Wennborg2012-06-011-0/+11
| | | | | | | | | This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. llvm-svn: 157818
* X86: Rename the CLMUL target feature to PCLMUL.Benjamin Kramer2012-05-311-1/+1
| | | | | | | It was renamed in gcc/gas a while ago and causes all kinds of confusion because it was named differently in llvm and clang. llvm-svn: 157745
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-101-221/+290
| | | | llvm-svn: 156579
* Use ptr_rc_tailcall instead of GR32_TC.Jakob Stoklund Olesen2012-05-091-2/+3
| | | | | | | | | The getPointerRegClass() hook will return GR32_TC, or whatever is appropriate for the current function. Patch by Yiannis Tsiouris! llvm-svn: 156459
* X86: Don't emit conditional floating point moves on when targeting ↵Benjamin Kramer2012-04-271-5/+10
| | | | | | | | | | | | | | | pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! llvm-svn: 155704
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-031-0/+5
| | | | llvm-svn: 153935
* Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.Eli Friedman2012-03-061-13/+13
| | | | llvm-svn: 152136
* Make aliases for shld and shrd match gas. PR12173.Eli Friedman2012-03-051-14/+14
| | | | llvm-svn: 152014
* Add q suffix aliases for the fistp and fisttp mnemonics.Chad Rosier2012-02-271-0/+2
| | | | | | | rdar://10921670 PR11935 llvm-svn: 151543
* Add WIN_FTOL_* psudo-instructions to model the unique calling conventionMichael J. Spencer2012-02-241-0/+5
| | | | | | used by the Win32 _ftol2 runtime function. Patch by Joe Groff! llvm-svn: 151382
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-181-0/+1
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. llvm-svn: 150873
* Use the same CALL instructions for Windows as for everything else.Jakob Stoklund Olesen2012-02-161-1/+0
| | | | | | | The different calling conventions and call-preserved registers are represented with regmask operands that are added dynamically. llvm-svn: 150708
* Intel syntax: Fix parser match class to check memory operand size.Devang Patel2012-01-171-3/+3
| | | | llvm-svn: 148338
* Get rid of unused codegen-only instruction.Eli Friedman2012-01-161-3/+0
| | | | llvm-svn: 148239
OpenPOWER on IntegriCloud