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* AVX-512: Removed "z" suffix from AVX-512 instructions, since it is ↵Elena Demikhovsky2013-12-111-1/+2
| | | | | | | | | incompatible with GCC. I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions). llvm-svn: 197041
* Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar,Yunzhong Gao2013-10-161-1/+1
| | | | | | | | | bulldozer and piledriver. Support for the instruction itself seems to have already been added in r178040. Differential Revision: http://llvm-reviews.chandlerc.com/D1933 llvm-svn: 192828
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-141-0/+8
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. llvm-svn: 192567
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-091-2/+2
| | | | llvm-svn: 192283
* Remove underscores from TBM instruction names for consistency with other ↵Craig Topper2013-10-051-24/+24
| | | | | | instruction naming. llvm-svn: 192040
* Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns ↵Craig Topper2013-10-051-39/+20
| | | | | | are sufficient. llvm-svn: 192039
* Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into ↵Craig Topper2013-10-051-0/+6
| | | | | | (sub -2, x). llvm-svn: 192037
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-031-2/+2
| | | | llvm-svn: 191874
* Add patterns for selecting TBM instructions from logical operations. Patch ↵Craig Topper2013-10-031-16/+81
| | | | | | from Yunzhong Gao. llvm-svn: 191871
* BEXTR should be defined to take same type for bother operands.Craig Topper2013-10-011-1/+1
| | | | llvm-svn: 191728
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-271-0/+79
| | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-12/+15
| | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. llvm-svn: 190717
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-121-0/+1
| | | | | | | | | Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. llvm-svn: 190611
* Add neverHasSideEffects=1 on a couple move instructions.Craig Topper2013-09-081-1/+1
| | | | llvm-svn: 190259
* Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). ↵Craig Topper2013-09-021-0/+10
| | | | | | Fixes PR17028. llvm-svn: 189742
* Fixup BZHI selection to remove an unneeded zero extension.Craig Topper2013-08-301-9/+13
| | | | llvm-svn: 189656
* Remove unused X86andn_flag node.Craig Topper2013-08-301-1/+0
| | | | llvm-svn: 189654
* Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, ↵Craig Topper2013-08-301-0/+10
| | | | | | Y), -1)). Fixes PR17038. llvm-svn: 189653
* Remove some unnecessary PredicateMethod overrides. Add RenderMethod ↵Craig Topper2013-08-261-15/+19
| | | | | | overrides to remove forwarding in the X86AsmParser code itself. No functional change. llvm-svn: 189205
* Put some of the AVX-512 parsing stuff in a more consistent place with the ↵Craig Topper2013-08-251-7/+6
| | | | | | existing functions. llvm-svn: 189204
* First round of fixes for the x86 fixes for the x86 move accumulator from/to ↵Craig Topper2013-08-251-11/+39
| | | | | | | | | | | | | | memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
* Add hasSideEffects/mayLoad/mayStore flags to the X86 ↵Craig Topper2013-08-241-0/+11
| | | | | | moffs8/moffs16/moffs32/moffs64 versions of move. llvm-svn: 189182
* Remove trailing whitespace.Craig Topper2013-08-241-21/+21
| | | | llvm-svn: 189178
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-311-0/+1
| | | | | | | | | All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. llvm-svn: 187491
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-311-54/+54
| | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
* Fixed incorrect disassembly for MOV16o16a when using Intel syntax.Craig Topper2013-07-311-2/+2
| | | | | | Patch by Richard Mitton. llvm-svn: 187471
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-0/+35
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* Fix more Intel syntax issues with FP instruction aliases. Test cases coming ↵Craig Topper2013-07-261-8/+8
| | | | | | in a subsequent patch. llvm-svn: 187187
* Fix aliases for shrd/shld to handle Intel syntax properly. Also suppress ↵Craig Topper2013-07-241-13/+13
| | | | | | them from being used by the asm printer. llvm-svn: 187020
* Don't let x86 asm printer use the no operand movsd alias. It should use the ↵Craig Topper2013-07-231-1/+1
| | | | | | normal movsl instead. llvm-svn: 186924
* Revert r186907 to fix bots.Craig Topper2013-07-231-1/+1
| | | | llvm-svn: 186910
* Don't let x86 asm printer use the no operand movsd alias. It should use the ↵Craig Topper2013-07-231-1/+1
| | | | | | normal movsl instead. llvm-svn: 186907
* Add aliases to map 'imm, mem' form of x86 bts/btr/btc without a size suffix ↵Craig Topper2013-07-231-0/+7
| | | | | | | | to their 32-bit forms. This makes them consistent with 'bt' which already had this handling. gas has the same behavior. There have been discussions on the mailing list about determining size based on the immediate, but my goal here was just to remove the inconsistency. llvm-svn: 186904
* Explicitly don't let the asm printer use the clrb/w/l aliases for xor %reg, ↵Craig Topper2013-07-231-4/+4
| | | | | | | | %reg. It only didn't use it before because it seems InstAlias handling in the asm printer fails to count tied operands so it tried to find an xor with 2 operands instead of the 3 it wfails to count tied. llvm-svn: 186900
* Suppress argumentless aliases for some x86 FP operations from being used by ↵Craig Topper2013-07-231-14/+14
| | | | | | the asm writer. Prefer to use the explicit %st(1) form. llvm-svn: 186897
* Fix the move to/from accumulator register instructions that use a full 64-bitKevin Enderby2013-07-221-15/+27
| | | | | | | | absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
* Recommit r186813: More Intel syntax alias fixes. With the addition of ↵Craig Topper2013-07-221-28/+28
| | | | | | suppressing some of the aliases from being emitted by the asm printer. llvm-svn: 186869
* Revert "More Intel syntax alias fixes."Tim Northover2013-07-221-28/+28
| | | | | | This reverts commit r186813, which broke the bots. llvm-svn: 186818
* More Intel syntax alias fixes.Craig Topper2013-07-221-14/+14
| | | | llvm-svn: 186814
* More Intel syntax alias fixes.Craig Topper2013-07-221-28/+28
| | | | llvm-svn: 186813
* Add Intel variants to aliases for some FP instructions.Craig Topper2013-07-221-8/+8
| | | | llvm-svn: 186811
* Reverse operands for Intel syntax form of 'bt' alias.Craig Topper2013-07-221-1/+2
| | | | llvm-svn: 186809
* X86: POP*rmm: move address operand to (ins) from (outs).Ahmed Bougacha2013-06-301-3/+3
| | | | llvm-svn: 185292
* X86: Make the cmov aliases work with intel syntax too.Benjamin Kramer2013-06-131-21/+25
| | | | llvm-svn: 183907
* X86: Stop LEA64_32r doing unspeakable things to its arguments.Tim Northover2013-06-101-3/+2
| | | | | | | | | | | | Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. llvm-svn: 183693
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-011-2/+3
| | | | | | Very sorry, it was committed from the wrong branch by mistake. llvm-svn: 183070
* TMP: LEA64_32r fixingTim Northover2013-06-011-3/+2
| | | | llvm-svn: 183069
* [ms-inline asm] Fix a crasher when we fail on a direct match.Chad Rosier2013-05-101-2/+5
| | | | | | | | | | | | | | | | | | The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. llvm-svn: 181620
* [ms-inline asm] Apply the condition code mnemonic aliases to both the Intel andChad Rosier2013-04-181-1/+1
| | | | | | | AT&T dialect. Test case for r179804 as well. rdar://13674398 and PR13340. llvm-svn: 179813
* [asm parser] Add support for predicating MnemonicAlias based on the assemblerChad Rosier2013-04-181-64/+64
| | | | | | | | variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
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